## Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing (2004)

Venue: | in Proc. of the International Test Conf |

Citations: | 2 - 0 self |

### BibTeX

@INPROCEEDINGS{Khan04spectralanalysis,

author = {Omar Khan and Michael L. Bushnell},

title = {Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing},

booktitle = {in Proc. of the International Test Conf},

year = {2004},

pages = {67--76}

}

### OpenURL

### Abstract

Spectral generation of patterns, to excite the natural frequencies of a digital circuit, is highly effective in testing sequential circuits. We have created a hardware embodiment of the spectral test-pattern generator for built-in self-test (BIST). We present five new spectral response compactors SRC1-5 for BIST. Each analyzes the spectral content of circuit output responses, and accumulates their spectrum in one or more counters. The method has astonishing results. SRC1 never aliased for any faults in the ISCAS ’89 benchmarks. SRC2, a low-overhead version of SRC1, aliased slightly more than the multiple-input signature register (MISR), but used less hardware than the MISR. This new spectral BIST system has a 91.26 % shorter test sequence than for a conventional LFSR pattern generator and MISR system, with at least 8.42 % higher fault coverage. The benefits of this are drastically shorter test sequences, the elimination of scan-shifting sequences, much lower test power dissipation, and higher fault coverage. 1

### Citations

145 |
Built-in Test for VLSI, Pseudorandom Techniques
- Bardell, McAnney, et al.
- 1987
(Show Context)
Citation Context ... x n-2 h n-2 DFF dn-1 dn-2 d1 d0 Figure 2: Multiple Input Signature Register [3, 4] x h 1 DFF and fault-free circuit match. The aliasing probability is 2 −k , where k is the number of LFSR flip-flops =-=[2, 20]-=-. Bakalis et al. [1] used the addition of all PO values from the circuit (syndromes) as a signature. 3 BIST Signature Analysis Using the Hadamard Transform The Hadamard matrix is used to identify the ... |

52 |
Essentials of Electronic Testing
- Bushnell, Agrawal
- 2000
(Show Context)
Citation Context ...ompactors were used at each CUT output [12]. Aliasing occurs when the compacted responses of the faulty DFF x n-1 h n-1 DFF x n-2 h n-2 DFF dn-1 dn-2 d1 d0 Figure 2: Multiple Input Signature Register =-=[3, 4]-=- x h 1 DFF and fault-free circuit match. The aliasing probability is 2 −k , where k is the number of LFSR flip-flops [2, 20]. Bakalis et al. [1] used the addition of all PO values from the circuit (sy... |

29 | Mixed-mode BIST using embedded processors
- Hellebrand, Wunderlich
- 1996
(Show Context)
Citation Context ...test, each input has a probability of 0.5 of being 1. With hardware weights, we vary the input probabilities of generating 1 ′ s, to improve the fault coverage and shorten the tests. Hellebran et al. =-=[10]-=- proposed BIST using an embedded microprocessor. Giani et al. proposed testing sequential cores in a system-on-a-chip (SoC) [7], where they generate test patterns using a real-time program running on ... |

21 |
Signature Analysis: A New Digital Field Service Method,” Hewlett-Packard Journal
- Frohwerk
- 1977
(Show Context)
Citation Context ... but with shorter test sets having the same fault coverage. 2.3 Pattern Generation Hardware The linear feedback shift register (LFSR) is the most commonly used pseudo-random pattern generation method =-=[5]-=-. The LFSR is a modulo-2 autonomous linear sequential network, with unidirectional interconnections of D flip-flops and XOR gates. An n-stage maximum-length LFSR traverses 2 n − 1 non-zero distinct st... |

13 | Efficient Spectral Techniques for Sequential ATPG
- Giani, Sheng, et al.
- 2001
(Show Context)
Citation Context ...he Hadamard matrix as digital waves, each having a distinct frequency and phase shift. Column 1 of H(2) (1 1 1 1) is: Column 2 of H(2) (1 −1 1 −1) is: Figure 1: Wave Representation of Columns of H(2) =-=[6]-=- 2.2 Compaction-Based ATPG One testing technique is a combination of linear reverse order restoration (LROR) compaction and a sequence extending technique [14]. LROR is a static compaction scheme that... |

6 |
Transition count testing of combinational logic circuits
- Hayes
- 1976
(Show Context)
Citation Context ...gnals in the circuit output response R change during BIST. An advantage of transition count compaction is that |C(R)|, the number of bits to represent C(R), is |C(R)| ≤ ⌈log 2 |R|⌉. |R| = # bits in R =-=[8, 9]-=-. Savir [18] proposed exhaustive pattern generation, and response compaction using ones counting. He designed combinational circuits so that the signature was the syndrome, or the number of switching ... |

4 |
Test Response Compaction by an Accumulator Behaving as a Multiple Input Non-Linear Feedback Shift Register
- Bakalis, Nikolos, et al.
- 2000
(Show Context)
Citation Context ...te more vectors to extend the test set. Very high fault coverages are achieved with small vector sets for the ISCAS ’89 benchmark circuits. They showed how the following 8-bit stream is extended [6]: =-=[1, 0, 1, 1, 1, 0, 1, 0]-=- T . They replaced each 0 with a −1 and got: [1, −1, 1, 1, 1, −1, 1, −1] T . Next, the bit Paper 3.3 68 stream was left multiplied by an 8 × 8 Hadamard matrix, H(3), to obtain the spectral correlation... |

2 |
Signature Analysis of Multi-Output Circuits
- David
- 1984
(Show Context)
Citation Context ...ompactors were used at each CUT output [12]. Aliasing occurs when the compacted responses of the faulty DFF x n-1 h n-1 DFF x n-2 h n-2 DFF dn-1 dn-2 d1 d0 Figure 2: Multiple Input Signature Register =-=[3, 4]-=- x h 1 DFF and fault-free circuit match. The aliasing probability is 2 −k , where k is the number of LFSR flip-flops [2, 20]. Bakalis et al. [1] used the addition of all PO values from the circuit (sy... |

2 | Novel Spectral Techniques for Builtin Self-test in a System-on-a-Chip Enviornment - Giani, Hsiao, et al. |

1 |
Generation of Optimal Transition Count Tests
- Hayes
- 1978
(Show Context)
Citation Context ...gnals in the circuit output response R change during BIST. An advantage of transition count compaction is that |C(R)|, the number of bits to represent C(R), is |C(R)| ≤ ⌈log 2 |R|⌉. |R| = # bits in R =-=[8, 9]-=-. Savir [18] proposed exhaustive pattern generation, and response compaction using ones counting. He designed combinational circuits so that the signature was the syndrome, or the number of switching ... |