## On the acceleration of test generation algorithms (1983)

Venue: | IEEE Transactions on Computers |

Citations: | 148 - 2 self |

### BibTeX

@ARTICLE{Fujiwara83onthe,

author = {Hideo Fujiwara and Senior Member and Takeshi Shimono and Student Member},

title = {On the acceleration of test generation algorithms},

journal = {IEEE Transactions on Computers},

year = {1983},

volume = {32},

pages = {1137--1144}

}

### Years of Citing Articles

### OpenURL

### Abstract

Abstract-In order to accelerate an algorithm for test generation, it is necessary to reduce thenumber ofbacktracks in the algorithm and to shorten the process time between backtracks. In this paper, we consider several techniques to accelerate test generation and present a new test generation algorithm called FAN (fan-out-oriented test generation algorithm). It is shown that theFAN algorithm is faster and more efficient than thePODEM algorithm reported by Goel.We also present an automatic test generation system composed oftheFAN algorithm and the concurrent fault simulation. Experimental results on large combinational circuits ofup to 3000 gates demonstrate that the system performs test generation very fast and effectively. Index Terms-Combinational logic circuits, D-algorithm, decision tree, multiple backtrace, PODEM algorithm, sensitization, stuck faults, test generation. I.

### Citations

230 | An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
- Goel
- 1981
(Show Context)
Citation Context ...e LSSD-type circuits, it is sufficient to develop a fast and efficient test generation algorithm only for combinational circuits. Many test generation algorithms have been proposed over the years [4]-=-=[8]-=-, [11]. The most widely used is the D-algorithm reported by Roth [5]. However, it has been pointed out that the D-algorithm is extremely inefficient in generating tests for combinational circuits that... |

61 |
Controllability/Observability Analysis of Digital Circuits
- Goldstein
- 1979
(Show Context)
Citation Context ...sest to a primary output. In this heuristic, we can use other observability measures. Methods for determining controllability/observability measures are available in the published literature, such as =-=[10]-=-. In order to reduce thenumber ofbacktracks, it is important to find the nonexistence ofthe solution as soon as possible. In the "branch and bound" algorithm, when we find that there exists no solutio... |

30 |
The concurrent simulation of nearly identical digital networks. In Papers on Twenty-five years of electronic design automation (25 years of DAC
- Ulrich, Baker
- 1988
(Show Context)
Citation Context ...lgorithm is faster and more efficient than thePODEM algorithm over these circuits. We also present an automatic test generation system composed of theFAN algorithm and the concurrent fault simulation =-=[9]-=- which performs test generation very fast and effectively over the above large combinational circuits. II. ACCELERATION OFALGORITHM Now we assume that the readers are familiar with the Dalgorithm and ... |

20 |
Analyzing errors with the boolean difference
- Sellers, Hsiao, et al.
- 1968
(Show Context)
Citation Context ...these LSSD-type circuits, it is sufficient to develop a fast and efficient test generation algorithm only for combinational circuits. Many test generation algorithms have been proposed over the years =-=[4]-=--[8], [11]. The most widely used is the D-algorithm reported by Roth [5]. However, it has been pointed out that the D-algorithm is extremely inefficient in generating tests for combinational circuits ... |

13 |
A Logic Design Structure for LSI Testing
- Eichelberger, Williams
- 1977
(Show Context)
Citation Context ... the worst case, exponential with the size ofthe circuit. One approach toovercome this is to take several techniques known as design for testability. The techniques using shift registers such as LSSD =-=[2]-=-, Scan Path [3], etc., allow the test generation problem to be completely reduced to one ofgenerating tests for combinational circuits. Hence, for these LSSD-type circuits, it is sufficient to develop... |

12 | Testing for, and distinguishing between failures - Savir, Roth - 1982 |

6 | The complexity of fault detection: An approach to design for testability - Fujiwara, Toida - 1982 |

5 | 9-V algorithm for test pattern generation of combinational digital circuits - Cha, Donath, et al. - 1978 |

3 |
Test Generation Systems in Japan
- Funatsu, Wakatsuki, et al.
- 1975
(Show Context)
Citation Context ..., exponential with the size ofthe circuit. One approach toovercome this is to take several techniques known as design for testability. The techniques using shift registers such as LSSD [2], Scan Path =-=[3]-=-, etc., allow the test generation problem to be completely reduced to one ofgenerating tests for combinational circuits. Hence, for these LSSD-type circuits, it is sufficient to develop a fast and eff... |

1 |
Diagnosis ofautomata failures:A calculus and a method
- Roth
- 1966
(Show Context)
Citation Context ...nt test generation algorithm only for combinational circuits. Many test generation algorithms have been proposed over the years [4]-[8], [11]. The most widely used is the D-algorithm reported by Roth =-=[5]-=-. However, it has been pointed out that the D-algorithm is extremely inefficient in generating tests for combinational circuits that implement error corr&ction and translation functions. To improve th... |

1 | Test generation for combinational circuits by structure description functions - Kinoshita, Takamatsu, et al. - 1980 |