Ultra-fast noise immune CMOS threshold gates

Ultra-fast noise immune CMOS threshold gates (2000)

Cached

Download Links

[www.eecs.wsu.edu]

by Valeriu Beiu

Venue:	Proc. MWSCAS’2000
Citations:	8 - 4 self

BibTeX

@INPROCEEDINGS{Beiu00ultra-fastnoise,
    author = {Valeriu Beiu},
    title = {Ultra-fast noise immune CMOS threshold gates},
    booktitle = {Proc. MWSCAS’2000},
    year = {2000},
    pages = {1310--1313},
    publisher = {IEEE Press}
}

Bookmark

OpenURL

Abstract

Abstract—This paper details a systematic method for significantly improving the noise margins of very fast threshold gates. The method is based on adding nonlinear terms determined from the Boolean form of the threshold function to be implemented. Simulation results support our theoretical claims. Finally, two methods for drastically reducing the dissipated power of such threshold gates down to <50%, and respectively <10 % are also suggested. Index Terms—VLSI, CMOS integrated circuits, threshold logic, threshold gates, noise. I.

Citations

150	Threshold Logic and its Applications - Muroga - 1971
62	A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations - Shibata, Ohmi - 1992
51	Circuit Complexity and Neural Networks - Parberry - 1994
27	Depth-Size Tradeoffs for Neural Computation - Siu, Roychowdhury, et al. - 1991
26	Finite precision error analysis of neural network hardware implementations - Holt, Hwang - 1993
23	Cilingiroglu: A Capacitive Threshold-logic Gate - Ozdemir, Kepkep, et al. - 1996
22	On the size of weights required for linear-input switching functions - Myhill, Kautz - 1961
20	Neuron MOS Binary-Logic Integrated CircuitsPart II: Simplifying Techniques of Circuit Configration and their Practical Applications - Shibata, Ohmi - 1993
18	Threshold logic - Hu - 1965
12	Ganged CMOS: Trading standby power for speed - Schultz, Francis, et al. - 1990
9	Synthesis of Threshold Circuits for Certain Classes of Boolean Functions - Red'kin - 1970
9	Neural Networks, Approximation Theory, and Finite Precision Computation - Wray, Green - 1995
9	Switched-capacitor neural networks - Tsividis, Anastassiou - 1987
9	A symmetric CMOS NOR gate for high-speed applications - Johnson - 1988
8	The synthesis of networks from threshold elements - Neciporuk - 1964
7	The connectivity analysis of simple association –or– how many connections do you need - Hammerstrom - 1988
7	Threshold Gate Circuits Employing Field-Effect Transistors - Lerch
6	Deeper sparser nets can be optimal - Beiu, Makaruk - 1998
6	CMOS Threshold gate and networks for order statistic filtering - Lee, Jen - 1994
5	Array-based analog computation: Principles, advantages and limitations - Kramer - 1996
5	Switched Neural Networks - Tsividis - 1989
5	A versatile threshold logic gate - Stokman, Cot¸ofană, et al. - 1998
5	Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays - Belabbès, Guterman, et al. - 1996
5	driven threshold elements - Varshavsky - 1998
5	Circuit Arrangement for Realizing Logic Elements That Can be Represented by Threshold Value Equations - Prange, Thewes, et al.
4	Linear-Input Logic - Minnik - 1961
4	Optimal VLSI implementation of neural networks - Beiu - 1995
4	Network generality, training required, and precision required - Denker, Wittner - 1988
4	A purely capacitive synaptic matrix for fixed-weight neural networks - Çilingiroğlu - 1991
4	Threshold Logic Gate - Heightley
4	A CMOS binary adder using quaternary ganged-logic internal node - Schultz, Smith - 1989
4	Circuit to Perform Variable Threshold Logic - Goodwin-Johansson
4	On the circuit complexity of sigmoid feedforward neural networks - Beiu, Taylor - 1996
3	The Synthesis of Circuits from Threshold Elements - Lupanov - 1973
3	Capacitive synapses for microelectronic neural networks - Çilingiro˘glu - 1990
3	Programmable neural logic - Bohossian, Hasler, et al. - 1998
3	Neural logic: Theory and implementation - Bohossian - 1998
3	Threshold logic for integrated full adder and the like - Martin
3	Symmetrical input NOR/NAND gate circuit - Zuleeg, Notthoff
3	Neural Network Implementation of a Binary Adder - Jeong - 1991
3	Floating Point Adder Circuit Using Neural Network - Chung, Pack - 1997
3	Circuit for Comparing Two Electrical Quantities Provided by a First Neuron MOS Field Effect Transistor and a Reference Source - Thewes, Prange, et al.
2	VLSI Complexity of Threshold Gate COMPARISON - Beiu - 1996
2	A Bayesian Networks - Mehdi, Zair, et al.
2	Adaptive associative memory comprising synapses of CMOS transistors - Jeong - 1997
2	Digital multiplier employing CMOS transistors - Jeong - 1992
2	Programmable multilayer neural network - Chung, Lee
2	Beta-CMOS Artificial Neuron and Imlementability Limits - Varshavsky, Marakhovsky - 1999
2	Techniques for reduced power and increased speed in dynamic- and ratio-logic circuits - Kartschoke, Rohrer - 1996
2	Low power pre-discharged ratio logic - Kartschoke, Rohrer