## Generalized constraint generation in the presence of non-deterministic parasitics (1996)

Venue: | In Proc. IEEE International Conference on Computer Aided Design |

Citations: | 2 - 2 self |

### BibTeX

@INPROCEEDINGS{Charbon96generalizedconstraint,

author = {Edoardo Charbon and Paolo Miliozzi and Enrico Malavasi and Alberto L. Sangiovanni-vincentelli},

title = {Generalized constraint generation in the presence of non-deterministic parasitics},

booktitle = {In Proc. IEEE International Conference on Computer Aided Design},

year = {1996},

pages = {187--192}

}

### OpenURL

### Abstract

In a constraint-driven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in great part on the effectiveness and the generality of the constraint generation process. None of the existing approaches to the constraint generation problem however are suitable for a number of parasitic effects in active and passive devices due to non-deterministic process variations. To address this problem a novel methodology is proposed based on the separation of all variables associated with non-deterministic parasitics, thus allowing the translation of the problem into an equivalent one in which conventional constrained optimization techniques can be used. The requirements of the method are a well-defined set of statistical properties for all parasitics and a reasonable degree of linearity of the performance measures relevant to design. 1

### Citations

239 | Matching Properties of MOS Transistors
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Citation Context ...degradation onto constraints on the tolerance for each nondeterministic parasitic component. Since a relation generally exists between parasitic tolerance and layout geometry, as shown for example in =-=[9]-=-, it is therefore possible to generate physical constraints on the relative distances and/or orientations of the objects in the layout. The stochastic model is then used in a constrained optimization ... |

57 |
The generalized adjoint network and network sensitivities
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Citation Context ...ility function relates to the difficulty of meeting a bound on a class of performance measures. Such scheme has been proposed as an effective design methodology in a number of mixed-mode applications =-=[10]-=-. Inequality (3)i enforces all performance specifications simultaneously, while (3)ii insures that the constraints be feasible. Term 4K(p) in (3) represents the model of the performance degradation in... |

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Citation Context ...]. Sensitivities can also be used to generate a set of constraints on interconnect parasitics [3]. A number of techniques have been proposed for a constraint-based approach to the layoutof analog ICs =-=[3, 4, 5, 6, 7]-=-. In these approachesa constraint generator is used to map high-level performance specifications onto a set of bounds, which are then used during the synthesis phases to control layout parasitics. The... |

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Citation Context ...adation of circuit performance from nominal due to layout parasitics using performance sensitivities [1, 2]. Sensitivities can also be used to generate a set of constraints on interconnect parasitics =-=[3]-=-. A number of techniques have been proposed for a constraint-based approach to the layoutof analog ICs [3, 4, 5, 6, 7]. In these approachesa constraint generator is used to map high-level performance ... |

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Citation Context ...]. Sensitivities can also be used to generate a set of constraints on interconnect parasitics [3]. A number of techniques have been proposed for a constraint-based approach to the layoutof analog ICs =-=[3, 4, 5, 6, 7]-=-. In these approachesa constraint generator is used to map high-level performance specifications onto a set of bounds, which are then used during the synthesis phases to control layout parasitics. The... |

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10 | Generalized constraint generation for analog circuit design
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A Routing Methodology for Analog Integrated Circuits
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Citation Context ...]. Sensitivities can also be used to generate a set of constraints on interconnect parasitics [3]. A number of techniques have been proposed for a constraint-based approach to the layoutof analog ICs =-=[3, 4, 5, 6, 7]-=-. In these approachesa constraint generator is used to map high-level performance specifications onto a set of bounds, which are then used during the synthesis phases to control layout parasitics. The... |

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Use of performance sensitivities in analog cell layout
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Citation Context ...ates close enough to the operating point. Linearized models have been proposed to evaluate the degradation of circuit performance from nominal due to layout parasitics using performance sensitivities =-=[1, 2]-=-. Sensitivities can also be used to generate a set of constraints on interconnect parasitics [3]. A number of techniques have been proposed for a constraint-based approach to the layoutof analog ICs [... |

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Gyurcsik, "Use of Performance Sensitivities in Analog Cell Layout
- Gad-El-Karim, S
- 1991
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Citation Context ...ates close enough to the operating point. Linearized models have been proposed to evaluate the degradation of circuit performance from nominal due to layout parasitics using performance sensitivities =-=[1, 2]-=-. Sensitivities can also be used to generate a set of constraints on interconnect parasitics [3]. A number of techniques have been proposed for a constraint-based approach to the layout of analogICs [... |