Wireplanning in Logic Synthesis (1998)
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| Venue: | In Proc. Intl. Conf. on Computer-Aided Design |
| Citations: | 15 - 2 self |
BibTeX
@INPROCEEDINGS{Gosti98wireplanningin,
author = {Wilsin Gosti and Amit Narayan and Robert K. Brayton and Alberto L. Sangiovanni-vincentelli},
title = {Wireplanning in Logic Synthesis},
booktitle = {In Proc. Intl. Conf. on Computer-Aided Design},
year = {1998},
pages = {26--33},
publisher = {IEEE}
}
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Abstract
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conventional logic synthesis techniques can produce circuits which will have long paths even if placed optimally. Then, we characterize the conditions under which this can happen and propose logic synthesis techniques which produce circuits which are “better ” for placement. Our proposed approach still separates logic synthesis from physical design. 1
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