DMCA
Dynamic data scratchpad memory management for a memory subsystem with an mmu
| Venue: | In LCTES ’07: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools |
| Citations: | 11 - 4 self |
BibTeX
@INPROCEEDINGS{Cho_dynamicdata,
author = {Hyungmin Cho and Bernhard Egger and Jaejin Lee and Heonshik Shin},
title = {Dynamic data scratchpad memory management for a memory subsystem with an mmu},
booktitle = {In LCTES ’07: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools},
year = {},
publisher = {ACM Press}
}
Share
 |
 |
 |
 |
||
OpenURL
Abstract
In this paper, we propose a dynamic scratchpad memory (SPM) management technique for a horizontally-partitioned memory subsystem with an MMU. The memory subsystem consists of a relatively cheap direct-mapped data cache and SPM. Our technique loads required global data and stack pages into the SPM on demand when a function is called. A scratchpad memory manager loads/unloads the data pages and maintains a page table for the MMU. Our approach is based on post-pass analysis and optimization techniques, and it handles the whole program including libraries. The data page mapping is determined by solving an integer linear programming (ILP) formulation that approximates our demand paging technique. The ILP model uses a dynamic call graph annotated with the number of memory accesses and/or cache misses obtained by profiling. We evaluate our technique on thirteen embedded applications. We compare the results to a reference system with a 4-way set associative data cache and the ideal case with the same 4-way cache and SPM, where all global and stack data is placed in the SPM. On average, our approach reduces the total system energy consumption by 8.1 % with no performance degradation. This is equivalent to exploiting 60 % of the room available in energy reduction between the reference case and the ideal case. Categories and Subject Descriptors C.4 [Performance of Systems]: Design Studies; D.3.4 [Programming Languages]: Processors—code generation, compilers, optimization; D.4.2 [Operating
Keyphrases
memory subsystem dynamic data memory management ideal case data page stack page global data 4-way set associative data cache subject descriptor design study memory access page table dynamic scratchpad memory stack data post-pass analysis whole program data page mapping management technique total system energy consumption programming language cheap direct-mapped data cache ilp model performance degradation reference system optimization technique 4-way cache technique load dynamic call graph scratchpad memory manager energy reduction horizontally-partitioned memory subsystem cache miss reference case integer linear programming
