## Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing (2000)

Venue: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems |

Citations: | 22 - 2 self |

### BibTeX

@ARTICLE{Jiang00crosstalk-driveninterconnect,

author = {Iris Hui-ru Jiang and Yao-wen Chang and Jing-yang Jou},

title = {Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing},

journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems},

year = {2000},

volume = {19},

pages = {999--1010}

}

### Years of Citing Articles

### OpenURL

### Abstract

Abstract—Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm which can optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement and linear runtime, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1-MB memory and 19.4-min runtime to achieve the precision of within 1 % error on a SUN Sparc Ultra-I workstation. Index Terms—Deep submicrometer, gate sizing, interconnect, performance optimization, physical design, routing. I.

### Citations

8593 |
Introduction to Algorithms
- Cormen, Leiserson, et al.
- 2001
(Show Context)
Citation Context ... drivers, the source , and the sink . The index of a node is labeled such that if node is the input of node , then . For an acyclic directed graph, this indexing can be labeled by topological sorting =-=[9]-=- with runtime linear in the graph size. Hence, the index of the source is zero, and that of the sink is .For , index is referred to a gate, a wire, or an input driver. On the other hand, the set of ed... |

436 |
Circuits, Interconnections and Packaging for VLSI
- Bakoglu
- 1990
(Show Context)
Citation Context ...oupling capacitance is dominated not only by physical geometry, but also by switching conditions [16]. The influence of switching conditions can be explained by the Miller and the anti-Miller effects =-=[2]-=-. Assume that the physical coupling capacitance between two neighboring wires is . The Miller effect occurs when the adjacent wires switch in opposite directions. In this case, the equivalent coupling... |

411 |
Digital Integrated Circuits - A Design Perspective
- Rabaey
- 1996
(Show Context)
Citation Context ...affects the performance of a circuit, especially in the deep submicrometer regime. Noise is an unwanted variation which makes the behavior of a manufactured circuit deviate from the expected response =-=[19]-=-. The deleterious influences of noise can be classified into two categories. One is malfunctioning, which makes the logic values of nodes differ from what we desire; the other is timing change, which ... |

369 |
The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers
- Elmore
- 1948
(Show Context)
Citation Context ...m node to all reachable drivers; similarly, means the proper set containing all the nodes on the paths from node to all reachable loads. For instance, in Fig. 4, and . We adopt the Elmore delay model =-=[11]-=- to compute the delays of gates and wires. The delay of node is , where is the downstream capacitance of including self-loading. For the time being, is referred to the upstream resistance of node , wh... |

169 | Generic global placement and floorplanning
- Eisenmann, Johannes
- 1998
(Show Context)
Citation Context ...r concern of comparable importance to power, area, and timing in integrated circuits [22], [23]. While power, area, and timing have been extensively discussed in the recent literature, e.g., [3]–[7], =-=[10]-=-, [18], and [20], relatively less work has been done on noise. Noise profoundly affects the performance of a circuit, especially in the deep submicrometer regime. Noise is an unwanted variation which ... |

82 | Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
- Chen, Chu, et al.
- 1999
(Show Context)
Citation Context ...the delay of the critical path in any combinational subcircuit between two latch elements. Hence, we can focus on the combinational circuits. The way we interpret a circuit is similar to that used in =-=[5]-=-. Given a combinational circuit with primary inputs, primary outputs and gates/wires. The sizes of gates and wires can be changed according to our objectives. For the th primary input, , we have one c... |

51 |
Minimum crosstalk channel routing
- Gao, Liu
- 1993
(Show Context)
Citation Context ... coupling capacitance. Miscellaneous heuristics and techniques have been proposed to minimize the overlap length or to maximize the distance between the wires; these methods include track permutation =-=[12]-=-, [13] and wire spacing [21], [24], [26], etc. In fact, coupling capacitance is dominated not only by physical geometry, but also by switching conditions [16]. The influence of switching conditions ca... |

33 | High-Level Area and Power Estimation for VLSI Circuits
- Nemani, Najm
- 1997
(Show Context)
Citation Context ...ern of comparable importance to power, area, and timing in integrated circuits [22], [23]. While power, area, and timing have been extensively discussed in the recent literature, e.g., [3]–[7], [10], =-=[18]-=-, and [20], relatively less work has been done on noise. Noise profoundly affects the performance of a circuit, especially in the deep submicrometer regime. Noise is an unwanted variation which makes ... |

30 | Post Global Routing Crosstalk Risk Estimation and Reduction
- Xue, Kuh, et al.
- 1996
(Show Context)
Citation Context ...ristics and techniques have been proposed to minimize the overlap length or to maximize the distance between the wires; these methods include track permutation [12], [13] and wire spacing [21], [24], =-=[26]-=-, etc. In fact, coupling capacitance is dominated not only by physical geometry, but also by switching conditions [16]. The influence of switching conditions can be explained by the Miller and the ant... |

28 |
Fast performance-driven optimization for buffered clock trees based on lagrangian relaxation
- Chen, Chang, et al.
- 1996
(Show Context)
Citation Context ...erature for optimizing area, power, and/or delay, e.g., [3]–[7], etc. In the previous work, Lagrangian relaxation has been proven to be an effective approach for simultaneous performance optimization =-=[4]-=-–[6]; this fact encourages us to adopt the Lagrangian relaxation method for our problem. In this paper, based on Lagrangian relaxation, we present an algorithm which can optimally solve the simultaneo... |

28 | Timing- and crosstalk-driven area routing
- Tseng, Scheffer, et al.
- 2001
(Show Context)
Citation Context ...us heuristics and techniques have been proposed to minimize the overlap length or to maximize the distance between the wires; these methods include track permutation [12], [13] and wire spacing [21], =-=[24]-=-, [26], etc. In fact, coupling capacitance is dominated not only by physical geometry, but also by switching conditions [16]. The influence of switching conditions can be explained by the Miller and t... |

24 | Layout Techniques for Minimizing On-Chip Interconnect Self Inductance
- Massoud, Majors, et al.
- 1998
(Show Context)
Citation Context ...For example, two adjacent wires form a coupling capacitor and a mutual inductor. A voltage or a current change on one wire can thus interfere the signal on the other wire. The inductive effects [15], =-=[17]-=- must be considered as circuit frequencies increase above 500 MHz. Manuscript received February 3, 1999; revised January 1, 2000. The work of I. H.-R. Jiang and J.-Y. Jou was supported in part by the ... |

22 | Optimal Wire-Sizing Function With Fringing Capacitance Consideration
- Chen, Wong
- 1997
(Show Context)
Citation Context ...ure for optimizing area, power, and/or delay, e.g., [3]–[7], etc. In the previous work, Lagrangian relaxation has been proven to be an effective approach for simultaneous performance optimization [4]–=-=[6]-=-; this fact encourages us to adopt the Lagrangian relaxation method for our problem. In this paper, based on Lagrangian relaxation, we present an algorithm which can optimally solve the simultaneous c... |

16 | Gate sizing: a general purpose optimization approach
- Coudert
- 1996
(Show Context)
Citation Context ... a greater concern of comparable importance to power, area, and timing in integrated circuits [22], [23]. While power, area, and timing have been extensively discussed in the recent literature, e.g., =-=[3]-=-–[7], [10], [18], and [20], relatively less work has been done on noise. Noise profoundly affects the performance of a circuit, especially in the deep submicrometer regime. Noise is an unwanted variat... |

16 | Design methodologies for noise in digital integrated circuits
- Shepard
- 1998
(Show Context)
Citation Context ...WITH decreasing feature sizes, higher clock rates, and increasing interconnect densities, noise is getting a greater concern of comparable importance to power, area, and timing in integrated circuits =-=[22]-=-, [23]. While power, area, and timing have been extensively discussed in the recent literature, e.g., [3]–[7], [10], [18], and [20], relatively less work has been done on noise. Noise profoundly affec... |

15 | Unification of budgeting and placement
- Sarrafzadeh, Knol, et al.
- 1997
(Show Context)
Citation Context ...parable importance to power, area, and timing in integrated circuits [22], [23]. While power, area, and timing have been extensively discussed in the recent literature, e.g., [3]–[7], [10], [18], and =-=[20]-=-, relatively less work has been done on noise. Noise profoundly affects the performance of a circuit, especially in the deep submicrometer regime. Noise is an unwanted variation which makes the behavi... |

15 | Conquering noise in deep-submicron digital ics
- Shepard
- 1998
(Show Context)
Citation Context ...ecreasing feature sizes, higher clock rates, and increasing interconnect densities, noise is getting a greater concern of comparable importance to power, area, and timing in integrated circuits [22], =-=[23]-=-. While power, area, and timing have been extensively discussed in the recent literature, e.g., [3]–[7], [10], [18], and [20], relatively less work has been done on noise. Noise profoundly affects the... |

14 |
An exact algorithm for low power library-specific gate re-sizing
- Chen, Sarrafzadeh
- 1996
(Show Context)
Citation Context ...reater concern of comparable importance to power, area, and timing in integrated circuits [22], [23]. While power, area, and timing have been extensively discussed in the recent literature, e.g., [3]–=-=[7]-=-, [10], [18], and [20], relatively less work has been done on noise. Noise profoundly affects the performance of a circuit, especially in the deep submicrometer regime. Noise is an unwanted variation ... |

13 |
Operations Research: Applications and Algorithms - 3rd ed
- Winston
- 1993
(Show Context)
Citation Context ...therefore, is The corresponding Lagrangian relaxation subproblem is subject to 1: Minimize To solve the Lagrangian relaxation subproblem, we derive the optimality conditions by Kuhn–Tucker conditions =-=[25]-=-. Theorem 4: The optimality conditions on Lagrange multipliers are given by Proof: By Kuhn–Tucker conditions [25], if the optimal solution of the Lagrangian relaxation subproblem is the optimal soluti... |

10 | Crosstalk minimization using wire perturbations
- Saxena, Liu
- 1999
(Show Context)
Citation Context ...llaneous heuristics and techniques have been proposed to minimize the overlap length or to maximize the distance between the wires; these methods include track permutation [12], [13] and wire spacing =-=[21]-=-, [24], [26], etc. In fact, coupling capacitance is dominated not only by physical geometry, but also by switching conditions [16]. The influence of switching conditions can be explained by the Miller... |

7 |
Introduction to Operations Research 5th ed
- Hillier, Lieberman
- 1990
(Show Context)
Citation Context ...n the second stage, we minimize the inter-wire physical coupling capacitance by sizing wires. We formulate the constraints for physical coupling capacitance in a posynomial (positive polynomial) form =-=[14]-=-, which can optimally be solved by Lagrangian relaxation. The second stage not only deals with the crosstalk problem but also optimizes area, power and delay by sizing gates and wires. Gate and wire s... |

3 |
crosstalk switchbox routing
- “Minimum
- 1994
(Show Context)
Citation Context ...ing capacitance. Miscellaneous heuristics and techniques have been proposed to minimize the overlap length or to maximize the distance between the wires; these methods include track permutation [12], =-=[13]-=- and wire spacing [21], [24], [26], etc. In fact, coupling capacitance is dominated not only by physical geometry, but also by switching conditions [16]. The influence of switching conditions can be e... |

2 |
Interconnect inductance effects on delay and crosstalk for long on-chip nets with fast input slew rates
- Lee, Hill, et al.
- 1998
(Show Context)
Citation Context ...ires. For example, two adjacent wires form a coupling capacitor and a mutual inductor. A voltage or a current change on one wire can thus interfere the signal on the other wire. The inductive effects =-=[15]-=-, [17] must be considered as circuit frequencies increase above 500 MHz. Manuscript received February 3, 1999; revised January 1, 2000. The work of I. H.-R. Jiang and J.-Y. Jou was supported in part b... |

1 |
Impact of deep sub-micron technologies on physical design
- Marek-Sadowska
- 1998
(Show Context)
Citation Context ...; these methods include track permutation [12], [13] and wire spacing [21], [24], [26], etc. In fact, coupling capacitance is dominated not only by physical geometry, but also by switching conditions =-=[16]-=-. The influence of switching conditions can be explained by the Miller and the anti-Miller effects [2]. Assume that the physical coupling capacitance between two neighboring wires is . The Miller effe... |

1 | Wire delay in the presence of crosstalk,” in Int Workshop Timing Issues in the Specification and Synthesis of Digital Systems (TAU - Yee, Chandra, et al. - 1997 |