Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing (2000)
| Venue: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems |
| Citations: | 22 - 2 self |
BibTeX
@ARTICLE{Jiang00crosstalk-driveninterconnect,
author = {Iris Hui-ru Jiang and Yao-wen Chang and Jing-yang Jou},
title = {Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems},
year = {2000},
volume = {19},
pages = {999--1010}
}
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Abstract
Abstract—Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm which can optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement and linear runtime, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1-MB memory and 19.4-min runtime to achieve the precision of within 1 % error on a SUN Sparc Ultra-I workstation. Index Terms—Deep submicrometer, gate sizing, interconnect, performance optimization, physical design, routing. I.
