Asic hardware implementation of the idea nxt encryption algorithm
| Venue: | In IEEE International Symposium on Circuits and Systems |
| Citations: | 1 - 0 self |
BibTeX
@INPROCEEDINGS{Macchetti_asichardware,
author = {Marco Macchetti},
title = {Asic hardware implementation of the idea nxt encryption algorithm},
booktitle = {In IEEE International Symposium on Circuits and Systems},
year = {},
pages = {21--24}
}
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Abstract
Abstract — Symmetric-key block ciphers are often used to provide data confidentiality with low complexity, especially in the case of dedicated hardware implementations. IDEA NXT is a novel block cipher family, which has many interesting features and is targeted to multimedia streaming encryption. Different values can be assigned to the hardware architecture parameters in order to scale the security and the performance of the cipher. In this paper we implement the IDEA NXT algorithm in custom silicon, using a commercial technology library; different optimizations are applied in order to satisfy different constraints in terms of latency and area occupation, maintaining a high level of security. After giving an overview of the IDEA NXT design, a discussion of the implementation choices and trade offs is given, highlighting the similarities and the main differences with regards to other block ciphers. To the authors ’ knowledge this is the first paper describing such work. I.
