Abstract

BDDs (Binary Decision Diagrams) are often used to represent Boolean expressions in hardware synthesis, hardware and software verification and numerous other applica-tions. BDD computation, implemented using tree data structures with binary nodes, is inherently memory intensive, and therefore suffers from the von Neumann memory bottleneck. This thesis examines an approach which can speed up BDD computation through compression of the graphical structure, reducing the overhead of handling memory pointers, and thereby reducing memory access latency. The novel aspect of this work is that a compression technique is used which allows BDD computation directly on the compressed data without the overheads of compression and decompression. The need for such an approach is driven by technology in two ways: the increasing discrepancy between CPU and memory speeds, and the move towards larger (64 bit) memory architectures. The work applies graph enumeration techniques to classify graph topology using a structural identifier (SID) coding table, providing the basis for algorithms which generate compressed representations. The work uses these new representations to develop algorithms which can pre-calculate results for specific graph-traversal operations in Combination lookup tables (CLT). The work distinguishes itself from other methods of reducing BDD access latency, such as index based systems, by improving spatial locality and simplifying computation at the same time.

Citations