## Increase in delay uncertainty by performance optimization (2001)

Venue: | Proc. IEEE International Symposium on Circuits and Systems (ISCAS |

Citations: | 7 - 2 self |

### BibTeX

@INPROCEEDINGS{Hashimoto01increasein,

author = {Masanori Hashimoto and Hidetoshi Onodera},

title = {Increase in delay uncertainty by performance optimization},

booktitle = {Proc. IEEE International Symposium on Circuits and Systems (ISCAS},

year = {2001},

pages = {379--382}

}

### OpenURL

### Abstract

This paper discusses a statistical effect of performance optimization to uncertainty in circuit delay. Performance optimization has an effect of balancing the delay of each path in a circuit, i.e. the delay of long paths are shortened and the delay of short paths are lengthened. In these path-balanced circuits, the uncertainty in circuit delay, which are caused by delay calculation error, manufacturing variability, fluctuation of operating condition, etc., becomes worse by a statistical characteristic of delay. Thus, a highly-optimized circuit may not satisfy delay constraints. In this paper, we demonstrate some examples that uncertainty in circuit delay is increased by path-balancing, and we then raise a problem that performance optimization increases statisticallydistributed circuit delay. 1.

### Citations

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Citation Context ...ion methods slow down the blocks/cells, where the given timing constraints are not tight, in order to reduce power dissipation, such as gate/transistor sizing [2–6], multiple supply voltage technique =-=[7]-=-, multiple threshold voltV-380 #Paths 4000 3000 2000 1000 Power/Area Reduction Initial Optimized Delay Reduction 0 0 1 2 3 4 5 6 Path Delay[ns] Figure 3: Path-Balancing Effect Caused by Performance Op... |

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Citation Context ...V-380 #Paths 4000 3000 2000 1000 Power/Area Reduction Initial Optimized Delay Reduction 0 0 1 2 3 4 5 6 Path Delay[ns] Figure 3: Path-Balancing Effect Caused by Performance Optimization age technique =-=[8]-=- and so on. Therefore, circuits are modified by performance optimization such that long paths are shortened and short paths are lengthened. This operation that the delay times of many paths in the cir... |

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Citation Context ...d the path-balanced circuits(Figs. 6, 7, 8). So, setting a design margin to avoid the delay violation is difficult and seems not to be a good way. To avoid this problem, statistical delay calculation =-=[12]-=- and the performance optimization based on statistical delay model [1, 13] are desired. We then apply the statistical static timing analysis(SSTA) method [1] to the initial and optimized circuits. The... |

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Citation Context ...n to avoid the delay violation is difficult and seems not to be a good way. To avoid this problem, statistical delay calculation [12] and the performance optimization based on statistical delay model =-=[1, 13]-=- are desired. We then apply the statistical static timing analysis(SSTA) method [1] to the initial and optimized circuits. The circuits and the error modelssFrequency 1800 1600 1400 1200 1000 800 600 ... |

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Citation Context ...ay does not increase from the initial value. The optimization method used for the experiments is a heuristic method that reduces power dissipation greedily based on the result of sensitivity analysis =-=[6]-=-. Figs. 4 and 5 represent the distributions of path delay in the initial and optimized circuits. The number of paths whose path delays are close to the longest path delay increases drastically, which ... |

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Citation Context ...al Initial Optimized 0 7.1 7.15 7.2 7.25 7.3 7.35 7.4 7.45 7.5 Delay[ns] Figure 7: Circuit delay distributions under a delay error model of 3� =10%(dsp alu) timation error in simple gates is 5 to 23% =-=[11]-=-. In this gate delay model, the error model of 3� =15% might be a reasonable assumption. We guess that the model of 3� =5% corresponds to the delay calculation using well-designed look-up tables chara... |

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Citation Context ...time, when circuits are optimized for performance improvement. We finally introduce and evaluate a statistical static timing analysis method that can calculate statistically-distributed circuit delay =-=[1]-=-. This paper is organized as follows. Section 2 explains the statistical characteristic of circuit delay time. Section 3 shows the reason why performance optimization increases statistically-distribut... |

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