Robust Energy-Efficient Adder Topologies

DMCA

Robust Energy-Efficient Adder Topologies

Cached

Download Links

Other Repositories/Bibliography

DBLP

by Dinesh Patil , Omid Azizi , Mark Horowitz

Citations:

12 - 3 self

BibTeX

@MISC{Patil_robustenergy-efficient,
    author = {Dinesh Patil and Omid Azizi and Mark Horowitz},
    title = {Robust Energy-Efficient Adder Topologies},
    year = {}
}

OpenURL

Abstract

In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determine how architectural features and design techniques affect energy efficiency. Optimizing different adders for the supply and threshold voltages, and transistor sizing, we show that topologies with the least number of logic stages having an average fanin of two per stage, and fewest wires are most energy efficient. While a design with fully custom sizes can be extremely tedious to layout, we show that custom sizing can be used as a guide to group different gates in the design, resulting in a manageable layout overhead without significant loss of energy efficiency. 1.

Keyphrases

robust energy-efficient adder topology energy efficiency manageable layout overhead design technique adder topology custom size energy efficient significant loss transistor sizing architectural feature average fanin different adder 32-bit adder topology custom sizing threshold voltage group different gate energy-delay tradeoff curve logic stage

DMCA