## Improving the process-variation tolerance of digital circuits using gate sizing and statistical techniques (2005)

Venue: | in Design Automation and Test in Europe |

Citations: | 4 - 0 self |

### BibTeX

@INPROCEEDINGS{Neiroukh05improvingthe,

author = {Osama Neiroukh and Xiaoyu Song},

title = {Improving the process-variation tolerance of digital circuits using gate sizing and statistical techniques},

booktitle = {in Design Automation and Test in Europe},

year = {2005},

pages = {294--299}

}

### OpenURL

### Abstract

A new approach for enhancing the process-variation tolerance of digital circuits is described. We extend recent advances in statistical timing analysis into an optimization framework. Our objective is to reduce the performance variance of a technology-mapped circuit where delays across elements are represented by random variables which capture the manufacturing variations. We introduce the notion of statistical critical paths, which account for both means and variances of performance variation. An optimization engine is used to size gates with a goal of reducing the timing variance along the statistical critical paths. We apply a pair of nested statistical analysis methods deploying a slower more accurate approach for tracking statistical critical paths and a fast engine for evaluation of gate size assignments. We derive a new approximation for the max operation on random variables which is deployed for the faster inner engine. Circuit optimization is carried out using a gain-based algorithm that terminates when constraints are satisfied or no further improvements can be made. We show optimization results that demonstrate an average of 72 % reduction in performance variation at the expense of average 20% increase in design area. 1.

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Citation Context ... works in this field appeared in [12, 13, 14]. However, in the past few years statistical techniques for timing analysis of circuits have received tremendous focus with representative works including =-=[15, 16, 17]-=-. Static timing analysis relies on two operations for propagating timing through a network, sum and max. Performing these calculations on pdfs is more expensive computationally than their counterparts... |

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Citation Context ...ingly diminutive. Circuit optimization was done in [3] by using LANCELOT [4] but had severe limitation on circuit size and used unrealistic delay models. A concept of criticality of gates was used in =-=[5]-=- but did not address the variance of the timing path delays. A transistor level approach was presented in [6]. Several yield-specific techniques were presented in [7]. In this paper we present a uniqu... |

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Citation Context ...ch exhibit more manufacturing variability. Depending on target application of circuit, such a performance variance around the center can represent undesirable uncertainty that should be minimized. In =-=[18]-=-, reduction of uncertainty was shown to be a key strategy for designing leading edge industrial designs. Decreasing variance can increase the overall yield of a design. An example of this is optimizat... |

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