Abstract

Minimizing power dissipation is an important design require-ment for both portable and non-portable systems. In this work, we propose an architectural solution to the power problem that retains performance while reducing power The technique, known as Pipeline Balancing (PLB), dynamically tunes the resources of a general purpose processor to the needs of the program by mon-itoring performance within each program. We analyze metrics for triggering PLB, and detail instruction queue design and energy savings based on an extension of the Alpha 21264 processor Us-ing a detailed simulator, we present component and full chip power and energy savings for single and multi-threaded execution. Re-sults show an issue queue and execution unit power reduction of up to 23 % and 13%, respectively, with an average performance loss of 1 % to 2 %. 1.

Citations

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1	Copyright 1994,95,96,97 by University of New South Wales . . . . Author: Jerry Vochteloo and Gernot Heiser - unknown authors