Theory and Algorithm of Local-Refinement Based Optimization with Application to Device and Interconnect Sizing

Theory and Algorithm of Local-Refinement Based Optimization with Application to Device and Interconnect Sizing (1999)

Cached

Download Links

by Jason Cong , Lei He

Citations:

BibTeX

@MISC{Cong99theoryand,
    author = {Jason Cong and Lei He},
    title = {Theory and Algorithm of Local-Refinement Based Optimization with Application to Device and Interconnect Sizing},
    year = {1999}
}

Bookmark

OpenURL

Abstract

In this paper we formulate three classes of optimization problems: the simple, monotonically-constrained, and bounded CH-programs. We reveal the dominance property under the local refinement (LR) operation for the simple CH-program, as well as the general dominance property under the pseudo-LR operation for the monotonically-constrained CH-program and the extended-LR operation for the bounded CH-program. These properties enable a very efficient polynomial-time algorithm, using different types of LR operations to compute tight lower and upper bounds of the exact solution to any CH-program. We show that the algorithm is capable of solving many layout optimization problems in deep submicron IC and/or high-performance MCM/PCB designs. In particular, we apply...

Citations

842	Introduction to Linear and Nonlinear Programming - Luenberger - 1973
147	TILOS: A Posynomial Programming Approach to Transistor Sizing - Fishburn, Dunlop - 1985
137	Fastcap: A Multipole Accelerated 3-D Capacitance Extraction Program - Nabors, White - 1991
91	Optimal wire sizing and buffer insertion for low power and a generalized delay model - Lillis, Cheng, et al. - 1995
90	Performance optimization of VLSI interconnect layout - Cong, He, et al. - 1996
81	An exact solution to the transistor sizing problem for cmos circuits using convex optimization - Sapatnekar, Rao, et al. - 1993
59	Interconnect Design for Deep Submicron ICs - Cong, Pan, et al. - 1997
49	Simultaneous driver and wire sizing for performance and power optimization - Cong, Koh - 1994
48	Optimal wiresizing under the distributed Elmore delay model - Cong, Leung - 1995
38	Optimal wiresizing for interconnects with multiple sources - Cong, He - 1996
37	Geometric programming: methods, computations and applications - Ecker - 1980
36	Interconnect sizing and spacing with consideration of coupling capacitance - Cong, He, et al.
31	L.T.: A sequential quadratic programming approach to concurrent gate and wire sizing - Menezes, Baldick, et al. - 1995
24	Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation - Chen, Chang, et al. - 1996
22	Gamal, A.: Optimal wire and transistor sizing for circuits with nontree topology - Vandenberghe, Boyd, et al. - 1997
19	Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology - Cong, He, et al. - 1997
16	A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies - Xue, Kuh, et al. - 1996
16	Optimal Wire Sizing and Bu er Insertion for Low Power and a Generalized Delay Model - Lillis, Cheng, et al. - 1996
15	Simultaneous buffer and wire sizing for performance and power optimization - Cong, Koh, et al. - 1996
14	An e cient approach to simultaneous transistor and interconnect sizing - Cong, He - 1996
14	Wire sizing as a convex optimization problem: Exploring the area delay tradeoff - SAPATNEKAR - 1996
13	Simultaneous gate and interconnect sizing for circuit-level delay optimization - Menezes, Pullela, et al. - 1995
12	A New Approach to Simultaneous Buffer Insertion and Wire Sizing - Chu, Wong - 1997
10	A fast algorithm for optimal wire-sizing under Elmore delay model - Chen, Wong - 1996
10	Greedy wire-sizing is linear time - Chu, Wong - 1998
7	Simultaneous Transistor and Intercon� nect Sizing Based on the General Dominance Property�� UCLA Computer Science - Cong, He� - 1995
7	An efficient technique for device and interconnect optimization in deep submicron designs - Cong, He - 1998
7	Fast performance-driven optimization for bu ered clock trees based on Lagrangian relaxation - Chen, Chang, et al. - 1996
6	Modeling the "effective capacitance" for the RC interconnect of CMOS gates - Qian, Pullela, et al. - 1994
5	A New Approach to Simultaneous Bu er Insertion and Wire Sizing - Chu, Wong - 1997
5	Simultaneous bu er and wire sizing for performance and power optimization - Cong, Koh, et al. - 1996
4	A 12.7Mchip/s all-digital BPSK direct sequence spread-spectrum IF transceiver in 1.2m CMOS - Chien, Yang, et al. - 1994
4	Analysis and justi cation of a simple, practical 2 1/2-d capacitance extraction methodology - Cong, He, et al. - 1997
2	available at http://cadlab.cs.ucla.edu/ ~helei/publications.html - Cong, He, et al. - 1998
2	Theory and algorithm of local re nement based optimization with application to transistor and interconnect sizing," Tech. Rep. 970034 (available at http://cadlab.cs.ucla.edu/ ~helei/publications.html), UCLA CS Dept - Cong, He - 1997
2	A sensitivity-based wiresizing approach tointerconnect optimization of lossy transmission line topologies - Xue, Kuh, et al. - 1996
1	Modeling the \e ective capacitance" for the RC interconnect of CMOS gates - Qian, Pullela, et al. - 1994