An Efficient Approach To Simultaneous Transistor And Interconnect Sizing

An Efficient Approach To Simultaneous Transistor And Interconnect Sizing (1996)

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by Jason Cong , Lei He

Venue:	IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN
Citations:	14 - 9 self

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@INPROCEEDINGS{Cong96anefficient,
    author = {Jason Cong and Lei He},
    title = {An Efficient Approach To Simultaneous Transistor And Interconnect Sizing},
    booktitle = {IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN},
    year = {1996},
    pages = {181--186},
    publisher = {}
}

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Abstract

In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CH-posynomial programs and reveal a general dominance property for all CH-posynomial programs (Theorem 1). We show that the STIS problems under a number of transistor delay models are CH-posynomial programs and propose an efficient and near-optimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buffer and wire sizing problem for real designs, it reduces the maximum delay by up to 17.7%, and more significantly, reduces the power consumption by a factor of 61.6%, when compared with the original designs. When used to solve the transistor sizing problem, it achieves a smooth area-delay trade-off. Moreover, the algorithm optimizes a clock net of 367 drivers/buffers and 59304m-long wire in 120 seconds, and a 32bit adder with 1,026 transistors in 66 seconds on a SPARC-5 workstation.

Citations

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