## Temperature-Aware Performance and Power Modeling (2004)

Venue: | In Technical Report 04-250, UCLA Engr |

Citations: | 11 - 0 self |

### BibTeX

@TECHREPORT{Liao04temperature-awareperformance,

author = {Weiping Liao and Lei He and Kevin Lepak},

title = {Temperature-Aware Performance and Power Modeling},

institution = {In Technical Report 04-250, UCLA Engr},

year = {2004}

}

### OpenURL

### Abstract

Power has become the primary design constraint for systems ranging from server computers to handhelds. As semiconductor technology scales down, leakage power becomes significant. Leakage power is exponentially dependent on temperature. Therefore, future design studies call for temperature-aware power modeling and coupled power and thermal management due to the temperature dependence of leakage power. Additionally, temperature-aware performance modeling must be carried out with coupled power and thermal management because circuit delay also depends on temperature. In this paper we study microarchitecture-level temperature-aware power and performance modeling. We present a leakage power model with temperature and voltage scaling.

### Citations

1680 | The SimpleScalar Tool Set, Version 2.0
- Burger, Austin
- 1997
(Show Context)
Citation Context ...endence for leakage power. System performance, on one hand, is affected by Vdd scaling because circuit delay and the maximum system clock frequency depend on Vdd [11]. Existing performance simulators =-=[12]-=-, [13] use instructions per cycle (IPC) to represent performance and do not consider changes in clock frequency possible with different Vdd. This approach is no longer valid with Vdd scaling, consider... |

1098 | Wattch: A framework for architectural-level power analysis and optimizations
- Brooks, Tiwari, et al.
- 2000
(Show Context)
Citation Context ...y formula (1) to calculate the leakage power for logic circuits. Table VII summarizes the power consumption for all components in our system. Similar to other Microarchitecture level power simulators =-=[6]-=-, [23], we do not consider the control logic as one component. We choose the floorplan similar to DEC Alpha 21364 [23] as shown in Figure 4. The thermal model extracts the thermal resistance Rt and th... |

469 |
Circuits, Interconnects and Packaging for VLSI
- Bakoglu
- 1990
(Show Context)
Citation Context ...hniques can help to reduce system thermal resistance, dissipate heat more quickly, and enable faster clocks. Novel cooling techniques include cooling studs, microbellows cooling, microchannel cooling =-=[30]-=- and direct water spray-cooling on electronic devices [31]. In this subsection, we consider two representative heatsink thermal resistances: (1) Rt = 0.8 o C/W for conventional air cooling, and (ii) R... |

360 | Temperature-Aware Microarchitecture: Modeling and Implementation
- Skadron, Stan, et al.
- 2004
(Show Context)
Citation Context ...al resistance Rt and thermal capacitance Ct are used to characterized thermal behavior. We develop our thermal calculation based on the equivalent RC thermal circuits presented in the HotSpot toolset =-=[23]-=-. As shown in Figure 3 from [23], the equivalent RC thermal circuit consists of three layers: heatsink, heat spreader and chip die. The chip die is partitioned into functional blocks according to micr... |

314 |
Design Challenges of Technology Scaling
- BORKAR
- 1999
(Show Context)
Citation Context ...latform, and that advanced cooling techniques can improve throughput significantly. I. INTRODUCTION Power has become a primary design constraint for systems ranging from server computers to handhelds =-=[1]-=-. For VLSI circuits, power consumption includes dynamic power and leakage power. As semiconductor technology keeps scaling down, leakage power grows significantly at the system level because of (1) in... |

165 | M.J.Irwin, “The design and use of simplepower: a cycle-accurate energy estimation tool
- Ye, Kandemir
- 2000
(Show Context)
Citation Context ...each technology generation [3]. The Intel Pentium IV processors running at 3GHz already have an almost equal amount of leakage and dynamic power [4]. Existing microarchitecture-level power simulators =-=[5]��-=-�[7] calculate leakage power by assuming a fixed ratio between dynamic and leakage power. This assumption is not accurate because dynamic power and leakage power scale differently as a function of Vdd... |

152 | A static power model for architects - Butts, Sohi - 2000 |

144 |
Design of High-Performance Microprocessor Circuits
- Chandrakasan, Bowhill, et al.
- 2001
(Show Context)
Citation Context ...d (2) the increasing number of idle modules in a highly integrated system. For current high-performance design methodologies, the contribution of leakage power increases at each technology generation =-=[3]. -=-The Intel Pentium IV processors running at 3GHz already have an almost equal amount of leakage and dynamic power [4]. Existing microarchitecture-level power simulators [5]–[7] calculate leakage powe... |

134 |
1-V Power supply high-speed digital circuit technology with multithreshold-voltage CMOS
- Mutoh
- 1992
(Show Context)
Citation Context ...ve power (Pa). (ii) standby mode, where a circuit is idle but ready to execute an operation, and dissipates only leakage power(Ps). (iii) inactive mode, where a circuit is deactivated by power gating =-=[15]-=- or other leakage reduction techniques, and dissipates a reduced leakage power defined as inactive power (Pi). A circuit in the inactive mode requires a non-negligible amount of time to wake up and th... |

129 | CACTI 3.0: An Integrated Cache Timing - Shivakumar, Jouppi - 2001 |

116 |
Fundamentals of modern VLSI devices
- Taur, Ning
- 1998
(Show Context)
Citation Context ...aling down, leakage power grows significantly at the system level because of (1) increase of device leakage current due to the reduction in threshold voltage, channel length, and gate oxide thickness =-=[2]-=-, and (2) the increasing number of idle modules in a highly integrated system. For current high-performance design methodologies, the contribution of leakage power increases at each technology generat... |

70 | Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks
- Chen
- 1998
(Show Context)
Citation Context ...· Vdd (1) Isub avg can be calculated by computing the average leakage current per gate for the given n circuits using gate-level estimation. Because leakage current depends on different input vectors=-= [18]-=-, we apply a genetic algorithm to obtain the input vectors for both maximum and minimum leakage currents, and then calculate I sub avg [17]. Figure 1 shows this I sub avg calculated with respect to th... |

31 |
et al., “A 600 MHz Superscalar RISC Microprocessor with Out-of-Order Execution
- Gieseke
- 1997
(Show Context)
Citation Context ... total component power consumption is the sum of power for all SRAM sub-arrays. Among logic circuits, for integer ALUs and FPUs, we take the area and gate count in the design of Alpha 21264 processor =-=[25]-=- and scale from 350nm technology down to 65nm technology. For all other logic circuits, we estimate gate count according to the designs in [26], and then apply formula (1) to calculate the leakage pow... |

28 | Analysis and minimization techniques for total leakage considering gate oxide leakage
- Lee, Kwong, et al.
(Show Context)
Citation Context ...In our experiment, dynamic energy in each clock cycle is calculated as CV 2 . In the rest of this subsection, we discuss our leakage power model with Vdd and temperature scaling. It has been shown in =-=[16]-=- that leakage power mainly consists of subthreshold and gate leakage power. Each type of leakage exhibits a different temperature and Vdd dependence. More importantly, the two manifest themselves at d... |

15 | Leakage power modeling and reduction with data retention
- Liao, Basile, et al.
- 2002
(Show Context)
Citation Context ... technology generation [3]. The Intel Pentium IV processors running at 3GHz already have an almost equal amount of leakage and dynamic power [4]. Existing microarchitecture-level power simulators [5]�=-=��[7]-=- calculate leakage power by assuming a fixed ratio between dynamic and leakage power. This assumption is not accurate because dynamic power and leakage power scale differently as a function of Vdd and... |

15 | Microarchitecture level power and thermal simulation considering temperature dependent leakage model
- LIAO, LI, et al.
- 2003
(Show Context)
Citation Context ...ed power/thermal management (DPTM) becomes necessary for accurate power estimation and appropriate power/thermal management. [8] presents a high-level leakage power model without temperature scaling. =-=[9] pro-=-poses a leakage power model with temperature scaling for 100nm technology with an empirical temperature-dependent term exp( −a T −b ) where a and b are empirical constants and T is the temperature... |

15 |
TEM 2 P 2 EST: a thermal enabled multi-model power/ performance ESTimator
- Dhodapkar, Lim, et al.
- 2000
(Show Context)
Citation Context ...temperature-dependent term exp( −a T −b ) where a and b are empirical constants and T is the temperature. Voltage scaling is not considered for either dynamic or leakage power in [9]. An earlier w=-=ork [10]-=- proposes chip-level thermal calculation similar to the universal mode in [9]. However, [10] does not consider temperature dependence for leakage power. System performance, on one hand, is affected by... |

10 | Topological analysis for leakage prediction on digital circuits
- Jiang, Tiwari, et al.
- 2002
(Show Context)
Citation Context ...using the same cell library. Also shown in Figure 1, the average difference between maximum and minimum I sub avg is about 60% of the minimum I sub avg . A formula similar to (1) has been proposed in =-=[19]-=- which explicitly considers the statistical impacts of transistor stacking. However, no explicit method is proposed in [18], [19] to consider voltage and temperature scaling. We characterize the 1sFig... |

8 |
Changing vectors of moore’s law
- Grove
- 2002
(Show Context)
Citation Context ...logies, the contribution of leakage power increases at each technology generation [3]. The Intel Pentium IV processors running at 3GHz already have an almost equal amount of leakage and dynamic power =-=[4]. -=-Existing microarchitecture-level power simulators [5]–[7] calculate leakage power by assuming a fixed ratio between dynamic and leakage power. This assumption is not accurate because dynamic power a... |

7 |
Enhanced Thermal Management by Direct Water Spray of High-Voltage, High Power Devices in a Three-Phase
- Shaw, Waldrop, et al.
- 2002
(Show Context)
Citation Context ...ipate heat more quickly, and enable faster clocks. Novel cooling techniques include cooling studs, microbellows cooling, microchannel cooling [30] and direct water spray-cooling on electronic devices =-=[31]-=-. In this subsection, we consider two representative heatsink thermal resistances: (1) Rt = 0.8 o C/W for conventional air cooling, and (ii) Rt = 0.067 o C/W for water spray-cooling in [31], which we ... |

5 |
Safe operating area and thermal design for MOSPOWER transistors,” Siliconix
- Severns
(Show Context)
Citation Context ...considering temperature-dependent leakage power. E. Thermal Runaway The thermal runaway problem in MOSFETs due to the positive feedback loop between on-resistance, temperature and power is well known =-=[28]-=-. In this section we will present another thermal runaway problem due to the interaction between leakage 8spower and temperature. As component temperature increases, its leakage power increases expone... |

4 |
Feedback Control System, 3rd Edition
- Vegte
- 1994
(Show Context)
Citation Context ...ax can be decided by (22): A. Thermal Model fmax ∝ (Vdd − Vt) 1.2 VddT 1.19 III. COUPLED POWER AND THERMAL SIMULATION According to the well-know duality between heat transfer and electrical phenom=-=ena [22]-=-, temperature can be modeled by equivalent RC thermal circuits, where two parameters: thermal resistance Rt and thermal capacitance Ct are used to characterized thermal behavior. We develop our therma... |

3 |
Temperature effects on mos transistors
- Cobbold
- 1966
(Show Context)
Citation Context ... voltage Vdd is delay ∝ Vdd/(Vdd − Vt) ξ , where Vt is the threshold voltage and α is an empirical constant. Temperature also affects circuit delay by affecting carrier mobility and threshold vo=-=ltage [21]. The dela-=-y model with temperature and voltage scaling is shown in (21): VddT µ delay ∝ (Vdd − Vt) ξ where µ and ξ are empirical constants for different technology. We obtain µ = 1.19 and ξ = 1.2 for ... |

1 | 2004b): “A General Equilibrium Model for Industries with Price and Service Competition,” Forthcoming in Operations Research
- unknown authors
- 2004
(Show Context)
Citation Context ...e is logic circuits such as functional units, the other is memory-based units such as caches and register files, modeled by SRAM arrays. For logic circuits, we use the leakage power model proposed in =-=[17]-=-. As shown in (1), for a given circuit, the leakage power can be calculated as the product of the number of gates (Ngate) and the average subthreshold leakage current per gate (I sub avg): Psub = Ngat... |

1 |
Palacharla and J.E.Smith, “Quantifying the complexity of superscalar processors
- S
- 1996
(Show Context)
Citation Context ...ea and gate count in the design of Alpha 21264 processor [25] and scale from 350nm technology down to 65nm technology. For all other logic circuits, we estimate gate count according to the designs in =-=[26]-=-, and then apply formula (1) to calculate the leakage power for logic circuits. Table VII summarizes the power consumption for all components in our system. Similar to other Microarchitecture level po... |