## Formal Verification of Digital Circuits Using Symbolic Ternary System Models (0)

Citations: | 24 - 6 self |

### BibTeX

@INPROCEEDINGS{Bryant_formalverification,

author = {Randal E. Bryant and Carl-Johan H. Seger},

title = {Formal Verification of Digital Circuits Using Symbolic Ternary System Models},

booktitle = {},

year = {},

pages = {121--146},

publisher = {American Mathematical Society}

}

### OpenURL

### Abstract

Ternary system modeling involves extending the traditional set of binary values f0; 1g with a third value X indicating an unknown or indeterminate condition. By making this extension, we can model a wider range of circuit phenomena. We can also efficiently verify sequential circuits in which the effect of a given operation depends on only a subset of the total system state.

### Citations

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(Show Context)
Citation Context ...generated by a set of Boolean variables. That is, each element of the algebra corresponds to a Boolean function over the variables. By representing these functions as Ordered Binary Decision Diagrams =-=[4]-=-, complex functions can be represented and manipulated efficiently. Of course, all of the verification properties we wish to decide require solving NP-hard problems. Our approach has a worst case time... |

1247 |
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Citation Context ...ior of an ALU on all possible inputs. By allowing only the most elementary of temporal operators, the class of properties we can express is relatively restricted, as compared to other temporal logics =-=[10, 17]-=-. In particular, we can only reason about circuit operations involving a bounded number of state transitions. Nonetheless, we have found that we can readily express many aspects of synchronous digital... |

1207 | Automatic verification of finitestate concurrent systems using temporal logic specifications
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Citation Context ...ior of an ALU on all possible inputs. By allowing only the most elementary of temporal operators, the class of properties we can express is relatively restricted, as compared to other temporal logics =-=[10, 17]-=-. In particular, we can only reason about circuit operations involving a bounded number of state transitions. Nonetheless, we have found that we can readily express many aspects of synchronous digital... |

431 |
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Citation Context ...g Data Stack First we will demonstrate the utility of the temporal notation in expressing phase level circuit timing and pipelining. The example is the nMOS stack circuit described by Mead and Conway =-=[16]-=-. Figure 1 shows the block diagram for the circuit. The circuit operates with a two-phase nonoverlapping clock. The stack command is specified by a pair of signals, OP1 and OP2, which are multiplexed ... |

179 |
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Citation Context .... 1.4. Related Work Our approach to verification relates most closely to the symbolic model checking algorithms devised by Bose and Fisher (BF) [2, 3], and by Burch, Clarke, McMillan, and Dill (BCMD) =-=[9]-=-. In fact, all of these approaches are implemented using the same Boolean manipulation code! Furthermore, Bose and Fisher implemented their checker by extending COSMOS. Despite these internal similari... |

103 |
Verification of sequential machines using boolean functional vectors
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(Show Context)
Citation Context ...ating representations of the individual next state functions for each state variable. Most other automated approaches to sequential circuit verification are based on testing state machine equivalence =-=[11, 13]-=-. Such methods are useful for comparing two different (but hopefully equivalent) representations of the system, such as one at a register-transfer level and one at a gate level. However, they do not w... |

90 |
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(Show Context)
Citation Context ...g based purely on testing implications is prone to this sort of "false positive" error. Problems of this sort have been encountered by people using other systems for hardware verification su=-=ch as HOL [14]-=- and EMC [10]. We believe that shortcomings of this sort can be corrected by more careful attention to the cases where an implication succeeds due a failure of its antecedent. In all of the verificati... |

63 | Boolean analysis of MOS circuits
- Bryant
- 1987
(Show Context)
Citation Context ...der Number 4976, and by the National Science Foundation, under grant number MIP-8913667. 1 in the course of normal circuit operation. This occurs frequently when modeling circuits at the switch-level =-=[6]-=-, due to (generally transient) short circuits or charge sharing. We can also deal with circuits in which indeterminate behavior occurs due either to timing hazards or to circuit oscillation. In all of... |

47 |
The Temporal Logic of
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- 1977
(Show Context)
Citation Context ...ior of an ALU on all possible inputs. By allowing only the most elementary of temporal operators, the class of properties we can express is relatively restricted, as compared to other temporal logics =-=[10, 17]-=-. In particular, we can only reason about circuit operations involving a bounded number of state transitions. Nonetheless, we have found that we can readily express many aspects of synchronous digital... |

29 |
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- 1990
(Show Context)
Citation Context ...tem model as a means of proving properties under a binary system model. 1.2. Contribution of Paper In earlier work, we demonstrated the utility of ternary modeling for verifying a variety of circuits =-=[1, 7]-=-. Our methodology is based on ternary simulation, either scalar or symbolic. With a simulator we can verify assertions specifying a postcondition on the circuit state that would result given some prec... |

27 |
Automatic Verification of Synchronous Circuits Using Symbolic Logic Simulation
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- 1989
(Show Context)
Citation Context ...ique weakest symbolic sequence satisfying the antecedent. Furthermore, the symbolic manipulations involve only variables explicitly mentioned in the assertion. Unlike other symbolic circuit verifiers =-=[3]-=-, we do not need to introduce extra variables denoting the initial circuit state or possible primary inputs. Finally, the length of the simulation sequence depends only on the depth of nesting of temp... |

23 |
On the Verification of Sequential Machines at Differing Levels of Abstraction
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- 1988
(Show Context)
Citation Context ...ating representations of the individual next state functions for each state variable. Most other automated approaches to sequential circuit verification are based on testing state machine equivalence =-=[11, 13]-=-. Such methods are useful for comparing two different (but hopefully equivalent) representations of the system, such as one at a register-transfer level and one at a gate level. However, they do not w... |

21 |
Verifying pipelined hardware using symbolic logic simulation
- Bose, Fisher
- 1989
(Show Context)
Citation Context ...ifier acceptable in most of the cases we have considered. 1.4. Related Work Our approach to verification relates most closely to the symbolic model checking algorithms devised by Bose and Fisher (BF) =-=[2, 3]-=-, and by Burch, Clarke, McMillan, and Dill (BCMD) [9]. In fact, all of these approaches are implemented using the same Boolean manipulation code! Furthermore, Bose and Fisher implemented their checker... |

12 | Formal verification of memory circuits by switch-level simulation
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(Show Context)
Citation Context ...tem model as a means of proving properties under a binary system model. 1.2. Contribution of Paper In earlier work, we demonstrated the utility of ternary modeling for verifying a variety of circuits =-=[1, 7]-=-. Our methodology is based on ternary simulation, either scalar or symbolic. With a simulator we can verify assertions specifying a postcondition on the circuit state that would result given some prec... |

12 |
On a Ternary Model of Gate Networks
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- 1979
(Show Context)
Citation Context ...scillation. In all of these cases, the modeling algorithm expresses this uncertainty by assigning value X to the offending circuit nodes, indicating that the actual digital value cannot be determined =-=[8, 15]-=-. As a second advantage, we can efficiently verify many aspects of digital circuit behavior by representing the circuit with a ternary system model. We do this by ternary symbolic simulation, in which... |

10 |
The Application of Program Verification Techniques to Hardware Verification
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- 1979
(Show Context)
Citation Context ...e system starts in some known initial state. In actual circuits, the initial state usually cannot be predicted. Other researchers have suggested symbolic simulation as a means of circuit verification =-=[12, 18]-=-. None of this work has presented a clear methodology for sequential circuit verification, however. 2. Ternary System Let B = f0; 1g be the set of the binary values and let T = f0; 1; Xg. The value X ... |

9 |
Modeling of Circuit Delays
- Seger, Bryant
- 1990
(Show Context)
Citation Context ...mum delay in any individual component of the circuit can be significantly larger. Thus we are not limited to unit delay circuit models. For example, by using the transformation technique described in =-=[19]-=-, both nominal delay and bounded delay circuit models can be used. The excitation function for a function node is often a ternary extension of a binary excitation function. Note that such an extension... |

8 |
A Three-Level Design Verification System
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- 1969
(Show Context)
Citation Context ...scillation. In all of these cases, the modeling algorithm expresses this uncertainty by assigning value X to the offending circuit nodes, indicating that the actual digital value cannot be determined =-=[8, 15]-=-. As a second advantage, we can efficiently verify many aspects of digital circuit behavior by representing the circuit with a ternary system model. We do this by ternary symbolic simulation, in which... |

8 |
COSMOS: a Compiled Simulator for
- Brayant, Beatty, et al.
- 1987
(Show Context)
Citation Context ...t eventuality cannot be expressed with our notation, unless the desired property is guaranteed to hold within a bounded time. 1.3. Overview of Implementation By modifying the COSMOS symbolic simulator=-=[5]-=-, we have been able to implement the algorithm described in this paper and to verify several full scale circuit designs. COSMOS represents a MOS circuit at the switch level as a network of transistor ... |

7 |
Fast Methods for Switch-Level Verification of MOS Circuits
- Reeves, Irwin
- 1987
(Show Context)
Citation Context ...e system starts in some known initial state. In actual circuits, the initial state usually cannot be predicted. Other researchers have suggested symbolic simulation as a means of circuit verification =-=[12, 18]-=-. None of this work has presented a clear methodology for sequential circuit verification, however. 2. Ternary System Let B = f0; 1g be the set of the binary values and let T = f0; 1; Xg. The value X ... |

5 |
COSMOS: a compiled simulator for MOS circuits," 24th Design Automation Conference
- Bryant, Beatty, et al.
- 1987
(Show Context)
Citation Context ...t eventuality cannot be expressed with our notation, unless the desired property is guaranteed to hold within a bounded time. 1.3. Overview of Implementation By modifying the COSMOS symbolic simulator=-=[5]-=-, we have been able to implement the algorithm described in this paper and to verify several full scale circuit designs. COSMOS represents a MOS circuit at the switch level as a network of transistor ... |

4 |
Verifying Pipelined Hardware Using
- Bose, Fisher
- 1989
(Show Context)
Citation Context ...ifier acceptable in most of the cases we have considered. 1.4. Related Work Our approach to verification relates most closely to the symbolic model checking algorithms devised by Bose and Fisher (BF) =-=[2, 3]-=-, and by Burch, Clarke, McMillan, and Dill (BCMD) [9]. In fact, all of these approaches are implemented using the same Boolean manipulation code! Furthermore, Bose and Fisher implemented their checker... |