• Documents
  • Authors
  • Tables
  • Log in
  • Sign up
  • MetaCart
  • DMCA
  • Donate

CiteSeerX logo

Advanced Search Include Citations
Advanced Search Include Citations | Disambiguate

DMCA

Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics (2004)

Cached

  • Download as a PDF

Download Links

  • [eda.ee.ucla.edu]
  • [eda.ee.ucla.edu]
  • [www.cs.york.ac.uk]
  • [www.cs.york.ac.uk]
  • [ballade.cs.ucla.edu]
  • [cadlab.cs.ucla.edu]
  • [cadlab.cs.ucla.edu]
  • [cadlab.cs.ucla.edu]
  • [cadlab.cs.ucla.edu]
  • [cadlab.cs.ucla.edu]

  • Other Repositories/Bibliography

  • DBLP
  • Save to List
  • Add to Collection
  • Correct Errors
  • Monitor Changes
by Fei Li , Yan Lin , Lei He , Jason Cong
Venue:FPGA'04
Citations:38 - 12 self
  • Summary
  • Citations
  • Active Bibliography
  • Co-citation
  • Clustered Documents
  • Version History

BibTeX

@MISC{Li04low-powerfpga,
    author = {Fei Li and Yan Lin and Lei He and Jason Cong},
    title = {Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics},
    year = {2004}
}

Share

Facebook Twitter Reddit Bibsonomy

OpenURL

 

Abstract

Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use pre-defined dual-Vdd and dual-Vt fabrics to reduce FPGA power. We design FPGA circuits with dual-Vdd/dual-Vt to e#ectively reduce both dynamic power and leakage power, and define dual-Vdd/dual-Vt FPGA fabrics based on the profiling of benchmark circuits. We further develop CAD algorithms including power-sensitivity based voltage assignment and simulated-annealing based placement to leverage such fabrics. Compared to the conventional fabric using uniform Vdd/Vt at the same target clock frequency, our new fabric using dual Vt achieves 9% to 20% power reduction. However, the pre-defined FPGA fabric using both dual Vdd and dual Vt only achieves on average 2% extra power reduction. It is because that the pre-designed dual-Vdd layout pattern introduces non-negligible performance penalty. Therefore, programmability of supply voltage is needed to achieve significant power saving for dual-Vdd FPGAs. To our best knowledge, it is the first in-depth study on applying both dual-Vdd and dual-Vt to FPGA considering circuits, fabrics and CAD algorithms.

Keyphrases

dual vt    dual-vdd dual-vt    dual vdd    fpga circuit    leakage power    target clock frequency    first in-depth study    cad algorithm    power reduction    benchmark circuit    dynamic power    dual-vt fabric    fpga power    uniform threshold voltage vt    dual-vdd fpgas    dual-vdd dual-vt fpga fabric    uniform vdd vt    supply voltage    extra power reduction    voltage assignment    pre-defined fpga fabric    significant power    conventional fabric   

Powered by: Apache Solr
  • About CiteSeerX
  • Submit and Index Documents
  • Privacy Policy
  • Help
  • Data
  • Source
  • Contact Us

Developed at and hosted by The College of Information Sciences and Technology

© 2007-2019 The Pennsylvania State University