## The Application of Formal Verification to SPW Designs (2003)

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Venue: | In Proceedings Euromicro Symposium on Digital System Design, IEEE Computer |

Citations: | 1 - 1 self |

### BibTeX

@INPROCEEDINGS{Akbarpour03theapplication,

author = {Behzad Akbarpour and Sofiène Tahar},

title = {The Application of Formal Verification to SPW Designs},

booktitle = {In Proceedings Euromicro Symposium on Digital System Design, IEEE Computer},

year = {2003},

pages = {325--332},

publisher = {Society Press}

}

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### Abstract

The Signal Processing WorkSystem (SPW) of Cadence is an integrated framework for developing DSP and communications products. Formal verification is a complementary technique to simulation based on mathematical logic. The HOL system is an environment for interactive theorem proving in a higher-order logic. It has an open user-extensible architecture which makes it suitable for providing proof support for embedded languages. In this paper, we propose an approach to model SPW descriptions at different abstraction levels in HOL based on the shallow embedding technique. This will enable the formal verification of SPW designs which in the past could only be verified partially using conventional simulation techniques. We illustrate this novel application through a simple case study of a Notch filter.

### Citations

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(Show Context)
Citation Context ... SPW design blocks into HOL and then complete the formal proof in the theorem proving environment. The HOL theorem prover is an interactive proof assistant for higher order logic, developed by Gordon =-=[3]-=-. It was explicitly designed for the formal verification of hardware, though it has also been applied to other areas including software verification and formalization of pure mathematics. HOL implemen... |

134 |
Rounding Errors in Algebraic Processes
- Wilkinson
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(Show Context)
Citation Context ...r and the user of a digital filter to be able to determine some measure of the error e n . A real number can be represented using a finite number of bits in either the fixedor the floating-point form =-=[10-=-]. The error introduced in such a representation is different in each case. Consider first the fixed-point format. Suppose a number v which has been normalized so that j v j 1 has the binary expansio... |

90 | cFormal Verification in Hardware Design: A Survey
- Kem, Greenstreet
- 1999
(Show Context)
Citation Context ... ratio due to the exponential number of test cases to be developed and verified. Therefore, new methods are needed for the economical and reliable verification of digital systems. Formal verification =-=[6]-=- has recently paved a path, showing the utility of finding bugs early in the design cycle. Formal verification techniques are usually classified in two categories [6]: interactive theorem proving and ... |

38 | Experience with embedding hardware description languages in HOL
- Boulton, Gordon, et al.
- 1992
(Show Context)
Citation Context ...ate levels, as predicates in higher-order logic. The process of specifying a hardware description language in higher-order logic is commonly known as semantic embedding. There are two main approaches =-=[2]-=-: deep embedding and shallow embedding. In deep embedding, the abstract syntax of a design description is represented by terms, Floating-Point Algorithm Fixed-Point Algorithm Test Bench Hardware Archi... |

28 |
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- 1993
(Show Context)
Citation Context ...es to model the design in each of these levels in higher-order logic within the HOL environment. The next step is to verify these different levels using a classical hierarchical proof approach in HOL =-=[7]-=-. Let X, Y and Z be the set of input and output signals and constant parametes corresponding to a typical design. Then, our final goal is to prove the following theorem in HOL: 8 X Y Z 9 Error. GATE_I... |

25 | Formal verification of floating point trigonometric functions - Harrison |

19 |
E ects of Finite Register Length in Digital Filtering and The Fast Fourier Transform
- Oppenheim, Weinstein
- 1972
(Show Context)
Citation Context ...nship: wn = M X k=0 b k xn k N X k=1 a k wn k (1) where fxn g is the input sequence and fwn g is the output sequence. There are three common sources of errors associated with the filter in (1) namely =-=[8]-=-: 1) Input quantization --- caused by the quantization of the input signal into a set of discrete levels. 2) Coefficient accuracy --- caused by the fact that the coefficients fa k g and fb k g are rea... |

6 |
Floating-point verification in HOL light: the exponential function
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(Show Context)
Citation Context ...vel and RTL (Register Transfer Level) descriptions into the logic. In addition, the extensive infrastructure of real analysis is essential to verify (or even state) the highest level of specification =-=[4]-=-. Finally, the adherence to a small set of primitive rules, gives us a high confidence that the final result is indeed valid. The rest of this paper is organized as follows: Section 2 describes the SP... |

3 |
Effects of Finite Register
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- 1972
(Show Context)
Citation Context ...ital filter specified by the input-output relationship: (1) where��is the input sequence and��is the output sequence. There are three common sources of errors associated with the filter in (1) namely =-=[8]-=-: 1) Input quantization — caused by the quantization of the input signal into a set of discrete levels.2) Coefficient accuracy — caused by the fact that the coefficients����and����are realized with f... |

2 | Formalization of Cadence SPW FixedPoint Arithmetic in HOL
- Akbarpour, Tahar, et al.
- 2002
(Show Context)
Citation Context ...e definition of the floating-point blocks, we used the formalization of the IEEE standard developed in [4]. For fixed-point blocks, we use the formalization of SPW fixed-point arithmetic developed in =-=[1]-=-. For the verification of the transition from floating-point to fixedpoint levels, the best approach is to establish an error analysis. When digital signal processing operations are implemented on a c... |