## Unrestricted vs restricted cut in a tableau method for Boolean circuits (2005)

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Venue: | In: AI&M 2004, 8th International Symposium on Artificial Intelligence and Mathematics |

Citations: | 20 - 4 self |

### BibTeX

@INPROCEEDINGS{Järvisalo05unrestrictedvs,

author = {Matti Järvisalo and Tommi A. Junttila and Ilkka Niemelä},

title = { Unrestricted vs restricted cut in a tableau method for Boolean circuits},

booktitle = {In: AI&M 2004, 8th International Symposium on Artificial Intelligence and Mathematics},

year = {2005},

pages = {373--399},

publisher = {}

}

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### Abstract

This paper studies the relative proof complexity of variations of a tableau method for Boolean circuit satisfiability checking obtained by restricting the use of the cut rule in several natural ways. The results show that the unrestricted cut rule can be exponentially more effective than any of the considered restrictions. Moreover, there are exponential differences between the restricted versions, too. The results also apply to the Davis-Putnam procedure for conjunctive normal form formulae obtained from Boolean circuits with a standard linear size translation.

### Citations

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Citation Context ...d tableau rules corresponds to the propagation induced by the unit-literal rule of the Davis-Putnam method for the clauses generated by the translation. 2 Boolean Circuits A Boolean circuit (see e.g. =-=[12]-=-) is an acyclic directed graph in which the nodes are called gates. The gates can be divided into three categories1 : (i) output gates with incoming edges but no outgoing edges; (ii) intermediate gate... |

1192 | Chaff: engineering an efficient SAT solver
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Citation Context ...state systems [2, 1]. The success builds on recent significant advances in the performance of SAT checkers based both on stochastic local search algorithms and on complete systematic search, see e.g. =-=[14, 11]-=-. Most successful satisfiability checkers assume that the input formulae are in conjunctive normal form (CNF). The reason for this is that it is simpler to develop efficient data structures and algori... |

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Citation Context ... basis of most ⋆ The financial support from Academy of Finland under grant 53695 is gratefully acknowledged.sstate-of-the-art Sat checkers today is the Davis-Putnam-Logemann-Loveland procedure (DPLL) =-=[10, 9]-=-. The efficiency of a typical DPLL based Sat checking system depends on – the applied search space pruning techniques, e.g., non-branching deduction rules, non-chronological backtracking (see e.g. [23... |

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Citation Context ...Ü� ��, and each Ü��� is a Boolean variable Ü��� with the interpretation “Ü��� � ØÖÙ� if and only if the � Ø� pigeon sits in the �Ø� hole”. When Ñ�Ò=-=, ÈÀÈ Ñ Ò is obviously unsatisfiable. For resolution [13], it was first proven by Haken [7] that-=- the proof complexity of ÈÀÈ Ò ���Ù Ò is exponential w.r.t. Ò. We define the size of a refutation in �� and its variations as �� � ���Ù Ø� ��� the number of node... |

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Citation Context ... basis of most ⋆ The financial support from Academy of Finland under grant 53695 is gratefully acknowledged.sstate-of-the-art Sat checkers today is the Davis-Putnam-Logemann-Loveland procedure (DPLL) =-=[10, 9]-=-. The efficiency of a typical DPLL based Sat checking system depends on – the applied search space pruning techniques, e.g., non-branching deduction rules, non-chronological backtracking (see e.g. [23... |

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Citation Context ...btained from Boolean circuits with a standard linear size translation. 1 Introduction Propositional satisfiability checkers have been applied successfully to many interesting domains such as planning =-=[10]-=- and model checking of finite state systems [2, 1]. The success builds on recent significant advances in the performance of SAT checkers based both on stochastic local search algorithms and on complet... |

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Citation Context ... 9]. The efficiency of a typical DPLL based Sat checking system depends on – the applied search space pruning techniques, e.g., non-branching deduction rules, non-chronological backtracking (see e.g. =-=[23]-=-), and conflict-driven learning (see e.g. [31]), and on – the splitting rule, i.e., on which Boolean variables to apply the explicit cut that induces branching, and what kind of heuristics is this dec... |

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Citation Context ...ves a satisfying truth assignment for the circuit, and a closed tableau indicates that the circuit is unsatisfiable. 4 Proof Complexity and the Pigeon-Hole Principle We use the notion of Ô-simulation=-= [3] to study t-=-he relative efficiency of proof systems. Let Ì be a proof system. The proof complexity (or complexity in short) of a proposition Ü in Ì is the minimum of �È �, where È is a Ì -proof of Ü an... |

310 |
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Citation Context ...mon subexpressions, while preserving natural structures and concepts of the domain. Boolean circuits can be translated into CNF using a standard translation often referred to as Tseitin’s translation =-=[30]-=-. This translation introduces a new variable for each gate in the circuit, resulting in a linear size CNF. In this work we are interested in solving Boolean circuit satisfiability problems using an ap... |

306 | Efficient conflict driven learning in a Boolean satisfiability solver
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Citation Context ...t checking system depends on – the applied search space pruning techniques, e.g., non-branching deduction rules, non-chronological backtracking (see e.g. [23]), and conflict-driven learning (see e.g. =-=[31]-=-), and on – the splitting rule, i.e., on which Boolean variables to apply the explicit cut that induces branching, and what kind of heuristics is this decision based on. For measuring the efficiency o... |

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Citation Context ...state systems [2, 1]. The success builds on recent significant advances in the performance of SAT checkers based both on stochastic local search algorithms and on complete systematic search, see e.g. =-=[14, 11]-=-. Most successful satisfiability checkers assume that the input formulae are in conjunctive normal form (CNF). The reason for this is that it is simpler to develop efficient data structures and algori... |

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Citation Context ...l NP-complete problem, see e.g. [26]. Because of its universal nature, a variety of important problems, e.g., in the areas of planning [19, 20], model checking of finite state systems [5, 4], testing =-=[22]-=-, and hardware verification [3], can be reduced to Sat. Due to this, there is a high demand for more feasible ways of solving Sat instances, ranging from industrial applications to pure research. Vari... |

269 |
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Citation Context ...ariable Ü��� with the interpretation “Ü��� � ØÖÙ� if and only if the � Ø� pigeon sits in the �Ø� hole”. When Ñ�Ò, ÈÀÈ Ñ Ò is obviously unsatisfiable. For re=-=solution [13], it was first proven by Haken [7] that the proof complexity of ÈÀÈ Ò-=- ���Ù Ò is exponential w.r.t. Ò. We define the size of a refutation in �� and its variations as �� � ���Ù Ø� ��� the number of nodes in the closed tableau. As an exa... |

193 |
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Citation Context ...akes efficient modelling of an application cumbersome. Fortunately, propositional formulas can be transformed in polynomial time into CNF while preserving the satisfiability of the instance, see e.g. =-=[27]-=-. Therefore one usually employs a more general formula representation in modelling and then transforms the formula into CNF. However, such a polynomial time translation introduces auxiliary variables ... |

154 | Bounded model checking using satisfiability solving
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Citation Context ...near size translation. 1 Introduction Propositional satisfiability checkers have been applied successfully to many interesting domains such as planning [10] and model checking of finite state systems =-=[2, 1]-=-. The success builds on recent significant advances in the performance of SAT checkers based both on stochastic local search algorithms and on complete systematic search, see e.g. [14, 11]. Most succe... |

135 | The quest for efficient Boolean Satisfiability Solvers. L.Zhang
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Citation Context ...re is a high demand for more feasible ways of solving Sat instances, ranging from industrial applications to pure research. Various methods for solving Sat instances have been developed (see [14] and =-=[32]-=- for surveys) and applied successfully to many interesting domains. Recognising the factors that affect the difficulty of satisfiability checking, i.e. the time needed to determine whether an instance... |

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Citation Context ...this, there is a high demand for more feasible ways of solving Sat instances, ranging from industrial applications to pure research. Various methods for solving Sat instances have been developed (see =-=[14]-=- and [32] for surveys) and applied successfully to many interesting domains. Recognising the factors that affect the difficulty of satisfiability checking, i.e. the time needed to determine whether an... |

75 |
Propositional proof complexity: Past, present and future
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Citation Context ...third approach, the one taken in this work, is to investigate how large the minimal-size proofs (refutations) are for different families of formulas. This measure is called proof complexity, see e.g. =-=[2]-=-. Proof complexity is of our interest as it allows one to differentiate heuristic performance from the proof rules in a method and to consider how small proofs can be established assuming optimal heur... |

67 |
A deterministic (2 − 2 k+1 )n algorithm for k-SAT based on local search
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Citation Context ...kers by experimental evaluation, i.e., investigate how long it takes for checkers to solve different types of instances. Another approach is worst-case analysis of SAT checking algorithms (see, e.g., =-=[8]-=-), i.e., giving analytic proofs of upper bounds on the running times of algorithms w.r.t. the instance size. A third approach, the one taken in this work, is to investigate how large the minimal-size ... |

63 | Combining strengths of circuit-based and CNF-based algorithms for high performance
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Citation Context ... 24] for interesting work in this direction. Another approach is to develop a generalisation of the DPLL method that works directly on the circuit structure. This direction has been pursued, e.g., in =-=[18, 21, 11, 29]-=-. Here we study the latter approach and use as the basis of the work a simplified version of a tableau method for Boolean circuit satisfiability checking that works directly with circuits [18] (see [1... |

62 | Finding bugs in an alpha microprocessor using satisfiability solvers
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Citation Context ...near size translation. 1 Introduction Propositional satisfiability checkers have been applied successfully to many interesting domains such as planning [10] and model checking of finite state systems =-=[2, 1]-=-. The success builds on recent significant advances in the performance of SAT checkers based both on stochastic local search algorithms and on complete systematic search, see e.g. [14, 11]. Most succe... |

60 | The efficiency of resolution and Davis-Putnam procedures
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Citation Context ...ofs can be simulated by tree-like resolution. This is fairly straightforward to establish from a well-known construction for reading a tree-like resolution refutation from a DPLL refutation, see e.g. =-=[1]-=-. Theorem 4. There is a polynomial p such that for any set of clauses ϕ, if there is a BC-refutation for C(ϕ) of size n, then there is a tree-like resolution refutation for ϕ of size p(n). Again, by t... |

54 | The taming of the cut. Classical refutations with analytic cut
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Citation Context ...chniques it employs a direct cut rule combined with deterministic (non-branching) deduction rules. The aim is to achieve high performance and to avoid some computational problems in cut free tableaux =-=[5]-=-. The efficiency of a typical Davis-Putnam method based SAT checking system depends on (i) the applied search space pruning techniques (e.g. non-branching deduction rules, non-chronological backtracki... |

51 | Circuit-based Boolean reasoning
- Kuehlmann, Ganai, et al.
- 2001
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Citation Context ...,23] for interesting work in this direction. Another approach is to develop a generalisation of the DPLL method that works directly on the circuit structure. This direction has been pursued, e.g., in =-=[11,18,21,29]-=-. Here we study the latter approach and use as the basis of the work a simplified version of a tableau method for Boolean circuit satisfiability checking that works directly with circuits [18] (see [1... |

44 | Tuning SAT Checkers for Bounded Model Checking
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Citation Context ... as they determine the values of all other gates. Therefore, the search space for a circuit with Ã gates and Æ input gates, Ã � Æ, would be Æ instead of Ã . This approach is proposed, for exam=-=ple, in [15, 6]-=-. However, our results show that doing so can, in the worst case, result in exponentially larger proofs compared to the unrestricted cut rule. In addition to the input gate restricted cuts, we study s... |

44 |
The intractability of resolution. Theoretical Computer Science 39:297–308
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Citation Context ...(li,j,li ′ ,j) | 1 � i<i ′ � n + 1, 1 � j � n } ∪ { li,j = not(xi,j) | 1 � i � n + 1, 1 � j � n } , where h1 1,2 ,...,hn n+1,n stands for all hj i,i ′,where1�i<i′ � n + 1and1�j � n. By the results in =-=[15]-=- we have the following theorem. Theorem 5. The size of the minimal resolution refutations for PHPn+1 n w.r.t. n. is exponential Combining theorem 4, corollary 2, and theorem 5, we have the following c... |

43 | Solving non-clausal formulas with DPLL search
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Citation Context ... 24] for interesting work in this direction. Another approach is to develop a generalisation of the DPLL method that works directly on the circuit structure. This direction has been pursued, e.g., in =-=[18, 21, 11, 29]-=-. Here we study the latter approach and use as the basis of the work a simplified version of a tableau method for Boolean circuit satisfiability checking that works directly with circuits [18] (see [1... |

38 |
Computational Complexity (AddisonWesley
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Citation Context ...positional satisfiability problem (SAT) of determining whether a given propositional formula has a truth assignment under which it evaluates to true is an archetypical NP-complete problem, see, e.g., =-=[26]-=-. Because of its universal nature, a variety of important problems, e.g., in the areas of planning [19,20], model checking of finite state systems [4,5], testing [22], and hardware verification [3], c... |

29 | Applying the Davis-Putnam procedure to non-clausal formulas
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- 2000
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Citation Context ...on circuits. One approach is to translate the circuit to CNF and use the clausal DPLL method as the basis but add extra information from the circuit to enhance the performance of the method. See e.g. =-=[13, 24]-=- for interesting work in this direction. Another approach is to develop a generalisation of the DPLL method that works directly on the circuit structure. This direction has been pursued, e.g., in [18,... |

25 | Simplification: A general constraint propagation technique for propositional and modal tableaux
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Citation Context ...tic (non-branching) deduction rules making it similar to the tableau system KE [7]. More information on the advantages of using a direct cut rule compared to typical cut free tableaux can be found in =-=[6, 7, 25]-=-. In this work we focus on the splitting/cut rule of the tableau method for Boolean circuits, the research problem being: How do restrictions on the use of the cut rule affect proof complexity in Bool... |

23 |
Handbook of Tableau Methods
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Citation Context ...r each Ús,a�Ú entry is added. The other nodes in the tree are entries of the form ÌÚ or �Ú, where Ú Î � . The entries are generated by applying the rules in Figure 2 as in the standard ta=-=bleau method [4]. A branch in the tableau is cont-=-radictory if it contains both �Ú � Ú � �Ò� �� �� �� � and ÌÚ entries for a gate Ú Î � . Otherwise, the branch is open. A branch is complete if it is contradictory, or ... |

22 | I.: Towards an efficient tableau method for Boolean circuit satisfiability checking
- Junttila, Niemelä
- 2000
(Show Context)
Citation Context ...ation can be simplified by sharing common subexpressions and by preserving natural structures and concepts of the domain. A tableau method that works directly with Boolean circuits has been developed =-=[9]-=-. It can be seen as a lifting of the Davis-Putnam procedure for CNF to Boolean circuits. Instead of standard (cut free) tableau techniques it employs a direct cut rule combined with deterministic (non... |

17 |
the Rest Will Follow: Exploiting Determinism in Planning as Satisfiability
- Act
- 1998
(Show Context)
Citation Context ... as they determine the values of all other gates. Therefore, the search space for a circuit with Ã gates and Æ input gates, Ã � Æ, would be Æ instead of Ã . This approach is proposed, for exam=-=ple, in [15, 6]-=-. However, our results show that doing so can, in the worst case, result in exponentially larger proofs compared to the unrestricted cut rule. In addition to the input gate restricted cuts, we study s... |

14 | Act, and the rest will follow: exploiting determinism in planning as satisfiability
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(Show Context)
Citation Context ...they determine the values of all other gates. Therefore, the search space for a circuit with K gates and N input gates, K � N, would be 2 N instead of 2 K . This approach is proposed, for example, in =-=[12,13,28]-=-. However, our results show that this kind of a restricted cut rule cannot polynomially simulate the unrestricted cut rule. In particular, we show that there is an infinite family {Cn} of circuits whi... |

11 |
ATPG: Boolean engines for formal hardware verification. Wolfgang Kunz
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Citation Context ...[26]. Because of its universal nature, a variety of important problems, e.g., in the areas of planning [19, 20], model checking of finite state systems [5, 4], testing [22], and hardware verification =-=[3]-=-, can be reduced to Sat. Due to this, there is a high demand for more feasible ways of solving Sat instances, ranging from industrial applications to pure research. Various methods for solving Sat ins... |

9 |
and ATPG: Boolean engines for formal hardware verification
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Citation Context ..., [26]. Because of its universal nature, a variety of important problems, e.g., in the areas of planning [19,20], model checking of finite state systems [4,5], testing [22], and hardware verification =-=[3]-=-, can be reduced to SAT. Due to this, there is a high demand for more feasible ways of solving SAT instances, ranging from industrial applications to pure research. Various methods for solving SAT ins... |

7 |
Christos Papadimitriou, Prabhakar Raghavan, and Uwe Schöning. A deterministic 22 − 2/(k + 1))n algorithm for k-SAT based on local search
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Citation Context ...eckers by experimental evaluation, i.e., investigate how long it takes for checkers to solve different types of instances. Another approach is worst-case analysis of Sat checking algorithms (see e.g. =-=[8]-=-), i.e., giving analytic proofs of upper bounds on the running times of algorithms w.r.t. the instance size. A third approach, the one taken in this work, is to investigate how large the minimal-size ... |

6 |
e Silva, “Solving satisfiability in combinational circuits
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(Show Context)
Citation Context ... circuits. One approach is to translate the circuit to CNF and use the clausal DPLL method as the basis but add extra information from the circuit to enhance the performance of the method. See, e.g., =-=[13,23]-=- for interesting work in this direction. Another approach is to develop a generalisation of the DPLL method that works directly on the circuit structure. This direction has been pursued, e.g., in [11,... |

6 |
On the complexity of derivation in propositional calculus. Automoted Reasontng(J
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Citation Context ...omain. Boolean circuitsM. Järvisalo et al. / Unrestricted vs restricted cut in a tableau method 375 can be translated into CNF using a standard translation often referred to as Tseitin’s translation =-=[30]-=-. This translation introduces a new variable for each gate in the circuit, resulting in a linear size CNF. In this work we are interested in solving Boolean circuit satisfiability problems using an ap... |

3 |
Junttila and Ilkka Niemelä. Towards an efficient tableau method for Boolean Circuit Satisfiability Checking
- Tommi
- 2000
(Show Context)
Citation Context ... 24] for interesting work in this direction. Another approach is to develop a generalisation of the DPLL method that works directly on the circuit structure. This direction has been pursued, e.g., in =-=[18, 21, 11, 29]-=-. Here we study the latter approach and use as the basis of the work a simplified version of a tableau method for Boolean circuit satisfiability checking that works directly with circuits [18] (see [1... |

3 |
Viresh Paruthi. Circuit-based boolean reasoning
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- 2001
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Citation Context |

1 |
BCSat 0.3 – a satisfiability checker for Boolean circuits. Computer program, 2001. Available at http://www.tcs.hut.fi/Software
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Citation Context ...9]. Here we study the latter approach and use as the basis of the work a simplified version of a tableau method for Boolean circuit satisfiability checking that works directly with circuits [18] (see =-=[17]-=- for an implementation of the method). The method is a non-clausal generalisation of DPLL to Boolean circuits which does not include learning or non-chronological backtracking techniques (see [29] for... |

1 |
Marques-Silva and Lus Guerra e Silva. Solving satisfiability in combinational circuits
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- 2003
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Citation Context ...on circuits. One approach is to translate the circuit to CNF and use the clausal DPLL method as the basis but add extra information from the circuit to enhance the performance of the method. See e.g. =-=[13, 24]-=- for interesting work in this direction. Another approach is to develop a generalisation of the DPLL method that works directly on the circuit structure. This direction has been pursued, e.g., in [18,... |

1 |
Tuning SAT checkers for bounded model checking, in: Computer Aided Verification
- Shtrichman
- 2000
(Show Context)
Citation Context ...they determine the values of all other gates. Therefore, the search space for a circuit with K gates and N input gates, K � N, would be 2 N instead of 2 K . This approach is proposed, for example, in =-=[12,13,28]-=-. However, our results show that this kind of a restricted cut rule cannot polynomially simulate the unrestricted cut rule. In particular, we show that there is an infinite family {Cn} of circuits whi... |