Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction

Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction (2003)

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by Rakesh Kumar , Keith I. Farkas , Norman P. Jouppi , Parthasarathy Ranganathan , Dean M. Tullsen

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161 - 11 self

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@INPROCEEDINGS{Kumar03single-isaheterogeneous,
    author = {Rakesh Kumar and Keith I. Farkas and Norman P. Jouppi and Parthasarathy Ranganathan and Dean M. Tullsen},
    title = {Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction},
    booktitle = {},
    year = {2003},
    pages = {81--92}
}

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Abstract

This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cores representing different points in the power/performance design space; during an application 's execution, system software dynamically chooses the most appropriate core to meet specific performance and power requirements.

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