Abstract

Forthcoming technology such as single-chip RISC/FPGA combinations make hardware compilation, fast prototyping, and FPGA replacement of ASICs all more likely. FPGAs have made a software-oriented approach to digital design feasible. This paper reviews remaining obstacles to this approach. The trade-os between use of an HDL and a `C'-variant, Handel-C, for logic synthesis are considered particularly in regard to programmability and the overall design process. A simple example in a likely application area, simulation/emulation of telecommunications switches, serves to illustrate the analysis. 1

Citations