## Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT (2004)

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Citations: | 18 - 5 self |

### BibTeX

@INPROCEEDINGS{Khomenko04logicsynthesis,

author = {Victor Khomenko and Maciej Koutny and Alex Yakovlev},

title = {Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT},

booktitle = {},

year = {2004},

pages = {16--25}

}

### Years of Citing Articles

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### Abstract

The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is deriving equations for logic gates implementing each output signal of the circuit. This is usually done using reachability graphs.

### Citations

1180 | Chaff: Engineering an efficient SAT solver
- Moskewicz, Madigan, et al.
(Show Context)
Citation Context ...h literal l being either a variable or the negation of a variable. It is assumed that no two literals in the same clause correspond to the same variable. Some of the leading SAT solvers, e.g., ZCHAFF =-=[12]-=-, can be used in the incremental mode, i.e., after solving a particular SAT instance the user can slightly change it (e.g., by adding and/or removing a small number of clauses) and execute the solver ... |

180 | An improvement of mcmillan’s unfolding algorithm
- Esparza, Römer, et al.
- 1996
(Show Context)
Citation Context ...-gate synthesis procedure based on state graphs. However, it often leads to state space explosion, and in our approach we follow another way of representing the behaviour of STGs, viz. STG unfoldings =-=[4, 5, 11]. A -=-finite and complete prefix of an STG’s unfolding is a finite acyclic net π which implicitly represents all the reachable states of Γ together with transitions enabled at those states. The set of p... |

162 |
Using Unfoldings to Avoid State Explosion Problem in the Verification of Asynchronous Circuits
- McMillan
(Show Context)
Citation Context ...-gate synthesis procedure based on state graphs. However, it often leads to state space explosion, and in our approach we follow another way of representing the behaviour of STGs, viz. STG unfoldings =-=[4, 5, 11]. A -=-finite and complete prefix of an STG’s unfolding is a finite acyclic net π which implicitly represents all the reachable states of Γ together with transitions enabled at those states. The set of p... |

147 |
Branching Processes of Petri Nets
- Engelfriet
- 1991
(Show Context)
Citation Context ...-gate synthesis procedure based on state graphs. However, it often leads to state space explosion, and in our approach we follow another way of representing the behaviour of STGs, viz. STG unfoldings =-=[4, 5, 11]. A -=-finite and complete prefix of an STG’s unfolding is a finite acyclic net π which implicitly represents all the reachable states of Γ together with transitions enabled at those states. The set of p... |

132 | The quest for efficient boolean satisfiability solvers
- Zhang, Malik
- 2002
(Show Context)
Citation Context ... is often much more efficient than solving these related instances as independent problems, because on the subsequent runs the solver can use some of the useful information (e.g., learnt clauses, see =-=[16]) -=-collected so far. In particular, such an approach can be used to compute projections of assignments satisfying a given formula, as described in sequel. Let V ⊆ Var be a non-empty set of variables oc... |

26 | A Unified Signal Transition Graph Model for Asynchronous Control Circuit SynTABLE
- Yakovlev, Lavagno, et al.
- 1996
(Show Context)
Citation Context ...nsition Graphs (STGs) is a formalism widely used for describing the behaviour of asynchronous control circuits. Typically, they are used as a specification language for the synthesis of such circuits =-=[2,3,14]-=-. STGs are a class of interpreted Petri nets, in which transitions are labelled with the names of rising and falling edges of circuit signals. Circuit synthesis based on STGs involves: (i) checking th... |

19 |
Verification and Synthesis of Asynchronous Control Circuits Using Petri Net Unfolding
- Semenov
- 1997
(Show Context)
Citation Context ... why various behavioural properties of Γ can be re-stated as the corresponding properties of π, and then checked, often much more efficiently (in particular, one can easily check the consistency of =-=Γ [13])-=-. One can show that the number of events in the complete prefix can never exceed the number of reachable states of Σ [5]. Moreover, complete prefixes are often exponentially smaller than the correspo... |

14 | Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
- Yakovlev
- 1998
(Show Context)
Citation Context ...rom the corresponding series used in [7] which have CSC. • CFSYMCSCA, CFSYMCSCB, CFSYMCSCC, CFSYMCSCD, CFASYMCSCA and CFASYMCSCB — control circuits for the Counterflow Pipeline Processor described=-= in [15]-=-. These are the same benchmarks as in [7]. Some of these STGs, although built by hand, are quite large in size. Two other groups, PPWKCSC(m,n) and PPARBCSC(m,n), contain scalable examples of STGs mode... |

12 | Detecting state coding conflicts in STG unfoldings using SAT
- Khomenko, Koutny, et al.
(Show Context)
Citation Context ...are descriptions. In order to alleviate this problem, Petri net analysis techniques based on causal partial order semantics, in the form of Petri net unfoldings, were applied to circuit synthesis. In =-=[7]-=-, we proposed a solution for one of the subproblems, central to the implementability analysis in step (i), viz. checking the Complete State Coding (CSC) condition. In essence, this problem consists in... |

10 | Token Ring Arbiters: an Exercise in Asynchronous Logic Design with Petri Nets
- Low, Yakovlev
- 1995
(Show Context)
Citation Context ...ntium T M IV/2.8GHz processor and 512M RAM. The first group of examples comes from real design practice. They are as follows: • LAZYRINGCSC and RINGCSC — Asynchronous Token Ring Adapters described=-= in [1, 9]. Th-=-ese two benchmarks were obtained from the LAZYRING and RING examples used in [7] by resolving CSC conflicts. • DUP4PHCSC, DUP4PHMTRCSC and DUPMTRMODCSC — control circuits for the Power-Efficient D... |

10 | and W.Vogler: An Improvement of McMillan’s Unfolding Algorithm - Esparza - 1996 |

9 | A Power-Efficient Duplex Communication System
- Furber, Efthymiou, et al.
- 2000
(Show Context)
Citation Context ...m the LAZYRING and RING examples used in [7] by resolving CSC conflicts. • DUP4PHCSC, DUP4PHMTRCSC and DUPMTRMODCSC — control circuits for the Power-Efficient Duplex Communication System described=-= in [6]. Th-=-ese are the benchmarks from the corresponding series used in [7] which have CSC. • CFSYMCSCA, CFSYMCSCB, CFSYMCSCC, CFSYMCSCD, CFASYMCSCA and CFASYMCSCB — control circuits for the Counterflow Pipe... |

7 | Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design
- Madalinski, Bystrov, et al.
(Show Context)
Citation Context ...algorithms achieved significant speedups compared with methods based on reachability graphs, and provided a basis for the framework for resolution of encoding conflicts (step (ii) above) described in =-=[10]-=-, which used the set of pairs of configurations representing encoding conflicts produced by the algorithm as an input.sHowever, those techniques would have limited practical impact if it was necessary... |

6 | Design and Evaluation of Two Asynchronous Token Ring Adapters
- Carrion, Yakovlev
- 1996
(Show Context)
Citation Context ...ntium T M IV/2.8GHz processor and 512M RAM. The first group of examples comes from real design practice. They are as follows: • LAZYRINGCSC and RINGCSC — Asynchronous Token Ring Adapters described=-= in [1, 9]. Th-=-ese two benchmarks were obtained from the LAZYRING and RING examples used in [7] by resolving CSC conflicts. • DUP4PHCSC, DUP4PHMTRCSC and DUPMTRMODCSC — control circuits for the Power-Efficient D... |

6 |
Chu: Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications
- -A
- 1987
(Show Context)
Citation Context ...nsition Graphs (STGs) is a formalism widely used for describing the behaviour of asynchronous control circuits. Typically, they are used as a specification language for the synthesis of such circuits =-=[2,3,14]-=-. STGs are a class of interpreted Petri nets, in which transitions are labelled with the names of rising and falling edges of circuit signals. Circuit synthesis based on STGs involves: (i) checking th... |

3 |
Lavagno L., Yakovlev A.: Logic synthesis of asynchronous controllers and interfaces
- Cortadella, Kishinevsky, et al.
- 2002
(Show Context)
Citation Context ...nsition Graphs (STGs) is a formalism widely used for describing the behaviour of asynchronous control circuits. Typically, they are used as a specification language for the synthesis of such circuits =-=[2,3,14]-=-. STGs are a class of interpreted Petri nets, in which transitions are labelled with the names of rising and falling edges of circuit signals. Circuit synthesis based on STGs involves: (i) checking th... |

1 | Koutny and A. Yakovlev: Logic Synthesis Avoiding State Space Explosion - Khomenko, M - 2003 |