Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

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Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 (2007)

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by Naveen Muralimanohar , Rajeev Balasubramonian , Norm Jouppi

Venue:	IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE
Citations:	122 - 18 self

BibTeX

@INPROCEEDINGS{Muralimanohar07optimizingnuca,
    author = {Naveen Muralimanohar and Rajeev Balasubramonian and Norm Jouppi},
    title = {Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0},
    booktitle = {IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE},
    year = {2007},
    pages = {3--14},
    publisher = {IEEE Computer Society}
}

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Abstract

A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor perfor- mance, power dissipation, and thermal management strategies. There are a number of interconnect design considerations that influence power/performance/area characteristics of large caches, such as wire mod- els (width/spacing/repeaters), signaling strategy (RC/differential/transmission), router design, etc. Yet, to date, there exists no analytical tool that takes all of these parameters into account to carry out a design space exploration for large caches and estimate an optimal organization. In this work, we implement two major extensions to the CACTI cache modeling tool that focus on interconnect design for a large cache. First, we add the ability to model different types of wires, such as RC-based wires with different power/delay characteristics and differential low-swing buses. Second, we add the ability to model Non-uniform Cache Access (NUCA). We not only adopt state-of-the-art design space exploration strategies for NUCA, we also enhance this exploration by considering on-chip network contention and a wider spectrum of wiring and routing choices. We present a validation analysis of the new tool (to be released as CACTI 6.0) and present a case study to showcase how the tool can improve architecture research methodologies.

Keyphrases

large cache wiring alternative nuca organization rc differential transmission on-chip network contention major extension l3 cache interconnect design consideration differential low-swing bus analytical tool validation analysis optimal organization state-of-the-art design space exploration strategy different power delay characteristic power dissipation thermal management strategy architecture research methodology case study new tool routing choice interconnect design wire mod el future microprocessor real estate design space exploration on-chip cache power performance area characteristic router design significant part non-uniform cache access wider spectrum different type processor perfor mance rc-based wire cactus cache

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