Abstract

As technology scaling poses a threat to DRAM scaling due to phys-ical limitations such as limited charge, alternative memory tech-nologies including several emerging non-volatile memories are be-ing explored as possible DRAM replacements. One main road-block for wider adoption of these new memories is the limited write endurance, which leads to wear-out related permanent fail-ures. Furthermore, technology scaling increases the variation in cell lifetime resulting in early failures of many cells. Existing er-ror correcting techniques are primarily devised for recovering from transient faults and are not suitable for recovering from permanent stuck-at faults, which tend to increase gradually with repeated write cycles. In this paper, we propose SAFER, a novel hardware-efcient multi-bit stuck-at fault error recovery scheme for resistive memo-ries, which can function in conjunction with existing wear-leveling techniques. SAFER exploits the key attribute that a failed cell with a stuck-at value is still readable, making it possible to continue to use the failed cell to store data; thereby reducing the hardware over-head for error recovery. SAFER partitions a data block dynamically while ensuring that there is at most one fail bit per partition and uses single error correction techniques per partition for fail recov-ery. SAFER increases the number of recoverable fails and achieves better lifetime improvement with smaller hardware overhead rela-tive to recently proposed Error Correcting Pointers and even ideal hamming coding scheme. Keywords multi-bit error correction, stuck-at fault recovery, reliability, write