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Clock Distribution Networks in Synchronous Digital Integrated Circuits (2001)
| Venue: | Proc. IEEE |
| Citations: | 82 - 7 self |
BibTeX
@INPROCEEDINGS{Friedman01clockdistribution,
author = {Eby G. Friedman},
title = {Clock Distribution Networks in Synchronous Digital Integrated Circuits},
booktitle = {Proc. IEEE},
year = {2001},
pages = {665--692}
}
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Abstract
this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path and the clock skew of that path are described in Section IV. The interplay among the aforementioned three subsystems making up a synchronous digital system is described in Section V; particularly, how the timing characteristics of the memory and logic elements constrain the design and synthesis of clock distribution networks. Different forms of clock distribution networks, such as buffered trees and H-trees, are discussed. The automated layout and synthesis of clock distribution networks are described in Section VI. Techniques for making clock distribution networks less sensitive to process parameter variations are discussed in Section VII. Localized scheduling of the clock delays is useful in optimizing the performance of high-speed synchronous circuits. The process for determining the optimal timing characteristics of a clock distribution network is reviewed in Section VIII. The application of clock distribution networks to high-speed circuits has existed for many years. The design of the clock distribution network of certain important VLSI-based systems has been described in the literature, and some examples of these circuits are described in Section IX. In an effort to provide some insight into future and evolving areas of research relevant to high-performance clock distribution networks, some potentially important topics for future research are discussed in Section X. Finally, a summary of this paper with some concluding remarks is provided in Section XI
Keyphrases
clock distribution network synchronous digital clock skew timing characteristic section vii high-speed synchronous circuit section iii synchronous system section xi many year buffered tree parameter variation local data path section ix section iv section vi clock delay fundamental definition section ii optimal timing characteristic section viii synchronous digital system logic element certain important vlsi-based system research relevant different form high-performance clock distribution network important topic future research localized scheduling separate focus high-speed circuit
