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Exploiting the on-chip inductance in high-speed clock distribution networks (2001)
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| Venue: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Citations: | 9 - 0 self |
BibTeX
@ARTICLE{Ismail01exploitingthe,
author = {Yehea I. Ismail and Eby G. Friedman and Jose L. Neves},
title = {Exploiting the on-chip inductance in high-speed clock distribution networks},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
year = {2001},
volume = {9},
pages = {963--973}
}
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Abstract
Abstract—On-chip inductance effects can be used to improve the performance of high-speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually eliminates short-circuit power consumption and reduces the area of the active devices and repeaters inserted to optimize the performance of long interconnects. These positive effects suggest the development of design strategies that benefit from on-chip inductance. An example of a clock distribution network is presented to illustrate the process in which inductance can be used to improve the performance of high-speed integrated circuits.
