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Modeling of Substrate Bias Effect in Bulk and (1995)
BibTeX
@MISC{P-mosfets95modelingof,
author = {So Sige-channel P-mosfets and Guo-fu Niu and Gang Ruan and Ting-ao Tang},
title = {Modeling of Substrate Bias Effect in Bulk and},
year = {1995}
}
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Abstract
This paper describes the effect of substrate bias in bulk and SO1 SiGe-channel y-MOSFETs. Applying a positive substrate bias to the bulk SiGe p-MOSFETs results in considerable shift of the SiGe channel threshold voltage towards more negative values, and considerable reduction of the saturated SiGe channel hole density, but has negligible effect on the surface channel threshold voltage and hole density. In SO1 SiGe p-MOSFETs, the threshold voltages and hole densities are all negligibly affected by the negative substrate bias. 1. Introductjon SiGe-channel p-MOSFETs have generated substantial research work because of higher mobility of holes confined to the SiGe channelrl-61. In earlier worksr4-51, the threshold voltages and hole densities for both the SiGe channel and the surface channel were studied by assuming a zero substrate bias. However, in application circuits, the pass transistors, differential input transistors, and series loadtdrive transistors in CMOS gates usually have non-zero substrate bias. Thus, this paper addresses the effect of substrate bias on the threshold voltages and hole densities. The bulk n+ gate SiGe channel
Keyphrases
hole density substrate bias substrate bias effect threshold voltage negligible effect pas transistor surface channel positive substrate bias application circuit sige channel threshold voltage towards negative substrate bias series loadtdrive transistor considerable shift sige channel hole density sige channelrl-61 so1 sige-channel y-mosfets so1 sige p-mosfets introductjon sige-channel p-mosfets surface channel threshold voltage non-zero substrate bias sige channel bulk gate sige channel differential input transistor negative value considerable reduction substantial research work bulk sige p-mosfets result cmos gate
