Logic BIST for large industrial designs: Real issues and case studies (1999)

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by Graham Hetherington , Tony Fryars , Nagesh Tamarapalli , Mark Kassab , Abu Hassan , Janusz Rajski
Citations:44 - 2 self

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32 Reducing Test Data Volume Using External/lbist Hybrid Test Patterns – Debaleena Das, Nur A. Touba - 2000
c ○ 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. Application of Deterministic Logic BIST on Industrial Circuits – Gundolf Kiefer, Hans-joachim Wunderlich, P. Prinetto - 2000
4 Combining deterministic logic bist with test point insertion – Harald Vranken, Florian Meister, Hans-joachim Wunderlich - 2002
38 Reducing Test Data Volume Using LFSR Reseeding with Seed Compression – C. V. Krishna, Nur A. Touba - 2002
1 Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets – Sunil R. Das, Made Sudarma, Mansour H. Assaf, Emil M. Petriu, Wen-ben Jone, Krishnendu Chakrabarty, Senior Member, Senior Member, Senior Member - 2003
2 Fault simulation and response compaction in full-scan circuits using HOPE – Sunil R. Das, Chittoor V. Ramamoorthy, Life Fellow, Life Fellow, Mansour H. Assaf, Emil M. Petriu, Wen-ben Jone, Mehmet Sahinoglu, Senior Member, Senior Member - 2002
Testing and Built-in Self-Test – A Survey – n.n.
A BIST GENERATOR CAD TOOL FOR NUMERIC INTEGRATED CIRCUITS – Chiraz Khedhiri, Mouna Karmani, Belgacem Hamdi
4 Spectral Methods for Testing of Digital Circuits – Nitin Yogi - 2009
3 Development of State Model Theory for External Exclusive NOR Type LFSR Structures – Afaq Ahmad
3 A scan BIST generation method using a Markov source and partial bit-fixing – Wei Li, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
The Case for a Configure-and-Execute Paradigm – Frank Vahid And, Frank Vahid, Tony Givargis - 1999
2 Test Data Compression: The System Integrator’s Perspective – Paul Theo Gonciari, Bashir M Al-hashimi - 2003
4 Integrated Test Data Decompression and Core Wrapper Design for Low-Cost Systemon-a-Chip Testing – Paul Theo Gonciari, Bashir M Al-hashimi - 2002
3 Reducing Synchronization Overhead in Test Data Compression Environments – Paul Theo Gonciari, Bashir M Al-hashimi - 2002
7 Achieving high Encoding Efficiency with partial dynamic LFSR Reseeding – C. V. Krishna, Abhijit Jas, Nur A. Touba - 2004
1 Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip – Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon Wang
18 The Case for a Configure-and-Execute Paradigm – Frank Vahid, Tony Givargis - 1999
2 SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling,” Proceedings of Design, Automation and Design No. of gates, no. of latches (1M, 100k) Initial given test data volume V i (Mbits – Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon Wang - 2007