CSDL: Reusable Computing System Descriptions for Retargetable System Software (2000)

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by Mark W. Bailey , John Knight , Ronald Williams
Citations:3 - 0 self

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6 Automatic Detection and Diagnosis of Faults in Generated Code for Procedure Calls – Jack W. Davidson, Mark W. Bailey, Mark W. Bailey - 2001
1 Construction of Systems Software Using Specifications of Procedure Calling Conventions – Mark W. Bailey, Jack W. Davidson - 1988
5 Target-Sensitive Construction of Diagnostic Programs for Procedure Calling Sequence Generators – Mark W. Bailey , Jack W. Davidson - 1996
Automatically Generating Back Ends for a Portable Assembly Language Using Declarative Machine Descriptions – João Dias, Norman Ramsey
2 Automatically Generating Instruction Selectors Using Declarative Machine Descriptions – João Dias, Norman Ramsey
1 Automatically Generating Back Ends Using Declarative Machine Descriptions – João Dias, Norman Ramsey
Jones). In preparation. – Thayer Rd, References Professor, Norman Ramsey, Professor Craig Chambers
1 Design Principles for Machine-Description Languages – Norman Ramsey, Jack W. Davidson, Mary F. Fernandez
8 Automatic Generation Of Data-Flow Analyzers: A Tool For Building Optimizers – Steven Weng-kiang Tjiang, Daniel Weise, Mike Smith, Bob Wilson - 1993
18 Automated Unique Input Output sequence generation for conformance testing of FSMs – Karnig Derderian, Robert M. Hierons, Mark Harman, Qiang Guo - 2006
5 Finite-State Code Generation – Christopher W. Fraser, et al. - 1999
244 Principles and methods of Testing Finite State Machines a survey. The – David Lee, Mihalis Yannakakis - 1996
17 Testing deterministic implementations from nondeterministic FSM specifications – A. Petrenko, N. Yevtushenko, G. V. Bochmann - 1996
39 A Design Environment for Addressing Architecture and Compiler Interactions – Jack W. Davidson, David B. Whalley - 1991
30 A Formal Model and Specification Language for Procedure Calling Conventions – Mark W. Bailey, Jack W. Davidson - 1994
3 Separating sequence overlap for automated test sequence generation – R. M. Hierons - 2006
(will be inserted by the editor) Estimating the feasibility of transition paths in Extended Finite State Machines – Karnig Derderian, Robert M. Hierons, Mark Harman, Qiang Guo, K. Derderian, R. M. Hierons, M. Harman, Q. Guo - 2009
36 Reduced Length Checking Sequences – Robert M. Hierons, Hasan Ural - 2002
7 The Zephyr Compiler Infrastructure – Andrew Appel, Jack Davidson, Norman Ramsey - 1998