Timing and Area Optimization for Standard-Cell VLSI Circuit Design (1995)


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by Weitong Chuang , Sachin S. Sapatnekar , Ibrahim N. Hajj
Citations:16 - 1 self

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198 Recent Directions in Netlist Partitioning: A Survey – Charles J. Alpert, Andrew B. Kahng
35 Partitioning very large circuits using analytical placement techniques – Bernhard M. Riess, Konrad Doll, Frank M. Johannes - 1994
30 A Hypergraph Framework For Optimal Model-Based Decomposition Of Design Problems – Nestor Michelena, Panos Papalambros - 1997
4 Multi-way partitioning via space lling curves and dynamic programming – C. J. Alpert, A. B. Kahng - 1994
15 Multi-Way Partitioning Via Geometric Embeddings, Orderings, and Dynamic Programming – Charles J. Alpert, Andrew B. Kahng - 1995
22 Multi-Way Partitioning Via Spacefilling Curves and Dynamic Programming – C. J. Alpert, A. B. Kahng - 1994
1 Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect – Franc Brglez, Baldomir Zajc
19 Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect – Franc Brglez, Baldomir Zajc - 1994
14 When Clusters Meet Partitions: A New Density Objective for Circuit Decomposition – J. -h. Dennis Huang, Andrew B. Kahng - 1994
19 Combining Problem Reduction and Adaptive Multi-Start: A New Technique for Superior Iterative Partitioning – Lars Hagen, Andrew B. Kahng - 1995
22 Optimal Model-Based Decomposition of Powertrain System Design – Nestor F. Michelena, Panos Y. Papalambros - 1995
27 On Implementation Choices for Iterative Improvement Partitioning Algorithms – Lars W. Hagen, Dennis J. -h. Huang, Andrew B. Kahng - 1997
9 Low-power architectural synthesis and the impact of exploiting locality – Renu Mehra, Lisa M. Guerra, Jan M. Rabaey - 1996
16 Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation – Jason Cong, Wilburt Labio, Narayanan Shivakumar - 1994
29 Acyclic Multi-Way Partitioning of Boolean Networks – Jason Cong, Zheng Li, Rajive Bagrodia - 1994
13 Delay And Area Optimization For Discrete Gate Sizes Under Double-Sided Timing Constraints – Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj - 1993
102 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
Novel Modeling and Optimization Techniques for Nano-Scale VLSI Designs – Sanghamitra Roy - 2008
12 Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization – Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn - 1995