Simultaneous Gate Sizing and Placement (2000)

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by Wei Chen , Cheng-ta Hsieh , Massoud Pedram
Venue:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Citations:9 - 1 self

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Freescale Semiconductor – Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma
5 An Integrated Logical and Physical Design Flow for Deep Submicron Circuits – Amir H. Salek, Jinan Lou, Massoud Pedram - 1999
5 Computing the Entire Active Area / Power Consumption versus Delay Trade-off Curve for Gate Sizing with a Piecewise Linear Simulator – Michel R.C.M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess - 1994
36 Optimal design of a CMOS op-amp via geometric programming – Maria Del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee - 2001
16 A New Statistical Optimization Algorithm for Gate Sizing – Murari Mani, Michael Orshansky
3 An Efficient Method for Large-Scale Gate Sizing – Siddharth Joshi, Stephen Boyd
Simultaneous Gate Sizing and Fanout Optimization – Wei Chen Cheng-Ta, Wei Chen, Cheng-ta Hsieh, Massoud Pedram - 2000
Analysis and Optimization under Crosstalk and Variability in Deep Sub-Micron VLSI Circuits – Debjit Sinha - 2006
11 A Computational Study of the Homogeneous Algorithm for Large-Scale Convex Optimization – Erling D. Andersen, Yinyu Ye - 1997
2 Complexity of Minimum-delay Gate Resizing – Supratik Chakraborty, Rajeev Murgai - 2001
1 On the Problem of Gate Assignment under Different Rise and Fall Delays – Arlindo L. Oliveira, Rajeev Murgai - 2003
10 Timing Driven Gate Duplication – Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh - 2004
Contents – Seng Oon Toh
Comparison of Gate Sizing Formulations and Solving Methods – Etienne Jacobs
26 New Algorithms for Gate Sizing: A Comparative Study – Olivier Coudert, Ramsey Haddad, S. Manne, Srilatha Manne - 1996
90 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
1 Layout driven timing optimization by generalized DeMorgan transform – Supratik Chakraborty, Rajeev Murgai
Power Minimization by Simultaneous Dual-V Assignment and Gate-sizing – Liqiong Wei, Kaushik Roy, Cheng-Kok Koh - 2000
Novel Modeling and Optimization Techniques for Nano-Scale VLSI Designs – Sanghamitra Roy - 2008