RC Interconnect Optimization under the Elmore Delay Model (1994)

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by Sachin S. Sapatnekar
Venue:Proc. ACM/IEEE Design Automation Conf
Citations:46 - 5 self

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6 Interconnect Design Using Convex Optimization – Piyush K. Sancheti, Sachin S. Sapatnekar - 1994
14 Wire Sizing as a Convex Optimization Problem: Exploring the Area-Delay Tradeoff – Sachin S. Sapatnekar - 1996
3 Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs – Jatan C. Shah, Sachin S. Sapatneka, Power-delay Tradeo S - 1996
7 An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs – Jason Cong, Lei He - 1997
1 Modeling and Layout Optimization of VLSI Devices and Interconnects in Deep Submicron Design – Jason Cong - 1997
5 Modeling and Optimization of VLSI Interconnects – Lei He - 1999
103 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
2 Optimal Design of Macrocells for Low Power and High Speed – Piyush K. Sancheti, Sachin S. Sapatnekar - 1996
9 Power vs. Delay in Gate Sizing: Conflicting Objectives? – Sachin S. Sapatnekar, Weitong Chuang - 1995
91 An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization – Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-mo Kang - 1993
7 Theory and Algorithm of Local-Refinement Based Optimization with Application to Device and Interconnect Sizing – Jason Cong, Lei He - 1999
25 Interconnect Estimation and Planning for Deep Submicron Designs – Jason Cong, David Zhigang Pan - 1998
7 Theory and Algorithm of Local-Refinement-Based Optimization with Application to Device and Interconnect Sizing – Jason Cong, Lei He - 1999
Wire Sizing Considering Skin Effect for High Frequency Circuits – Yoshihiro Nagano, Yun Cao, Akira Tsukizoe
Chip and Package Co-Design of Clock Networks – Qing Zhu, Wayne Wei-ming Dai, David Helmbold, Martine Schlag - 1995
12 Performance Driven Global Routing for Standard Cell Design – Jason Cong, Patrick H. Madden - 1997
6 Performance-Driven Routing with Multiple Sources – Jason Cong, Patrick H. Madden - 1997
Timing-Driven Interconnect Synthesis ∗ – Jiang Hu, Gabriel Robins, C. N. Sze
6 Wire Width Planning for Interconnect Performance Optimization – Jason Cong, Zhigang (David) Pan - 2002