RC Interconnect Optimization under the Elmore Delay Model (1994)

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by Sachin S. Sapatnekar
Venue:Proc. ACM/IEEE Design Automation Conf
Citations:50 - 5 self

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6 Interconnect Design Using Convex Optimization – P K Sancheti, S S Sapatnekar - 1994
104 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
14 Wire Sizing as a Convex Optimization Problem: Exploring the Area-Delay Tradeoff – Sachin S. Sapatnekar - 1996
3 Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs – Jatan C. Shah, Sachin S. Sapatneka, Power-delay Tradeo S - 1996
7 An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs – Jason Cong, Lei He - 1997
5 Modeling and Optimization of VLSI Interconnects – Lei He - 1999
1 Modeling and Layout Optimization of VLSI Devices and Interconnects in Deep Submicron Design – Jason Cong - 1997
91 An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization – Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-mo Kang - 1993
232 CACTI: An enhanced cache access and cycle time model – S J E Wilton, N P Jouppi - 1996