Wire Sizing as a Convex Optimization Problem: Exploring the Area-Delay Tradeoff (1996)

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by Sachin S. Sapatnekar
Venue:IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN
Citations:14 - 0 self

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4 Modeling and Optimization of VLSI Interconnects – Lei He - 1999
5 Interconnect Design Using Convex Optimization – Piyush K. Sancheti, Sachin S. Sapatnekar - 1994
2 Optimal Design of Macrocells for Low Power and High Speed – Piyush K. Sancheti, Sachin S. Sapatnekar - 1996
10 Power vs. Delay in Gate Sizing: Conflicting Objectives? – Sachin S. Sapatnekar, Weitong Chuang - 1995
90 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
81 An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization – Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-mo Kang - 1993
36 Optimal design of a CMOS op-amp via geometric programming – Maria Del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee - 2001
7 An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs – Jason Cong, Lei He - 1997
1 Simultaneous Allocation And Scheduling Using Convex Programming Techniques – Shankar Ramaswamy, Prithviraj Banerjee - 1995
7 Theory and Algorithm of Local-Refinement Based Optimization with Application to Device and Interconnect Sizing – Jason Cong, Lei He - 1999
7 Theory and Algorithm of Local-Refinement-Based Optimization with Application to Device and Interconnect Sizing – Jason Cong, Lei He - 1999
8 Power-Delay Optimizations in Gate Sizing – Sachin S. Sapatnekar, Weitong Chuang - 2000
41 RC Interconnect Optimization under the Elmore Delay Model – Sachin S. Sapatnekar - 1994
6 Algorithms for Performance Driven Design of Integrated Circuits – John Patrick Lillis, John Patrick Lillis - 1996
3 An Efficient Method for Large-Scale Gate Sizing – Siddharth Joshi, Stephen Boyd
19 Digital Circuit Optimization via Geometric Programming – Stephen P. Boyd, Seung-jean Kim, Dinesh D. Patil, Mark A. Horowitz - 2005
1 Modeling and Layout Optimization of VLSI Devices and Interconnects in Deep Submicron Design – Jason Cong - 1997
1 Macro-Driven Circuit Design Methodology for High-Performance Datapaths – Mahadevamurty Nemani, Vivek Tiwari - 2000
5 Convex Delay Models for Transistor Sizing – Mahesh Ketkar, Kishore Kasamsetty - 2000