The ALPBench Benchmark Suite for Complex Multimedia Applications (2005)

by Man-lap Li , Ruchira Sasanka , Sarita V. Adve , Yen-kuang Chen , Eric Debes
Venue:In Proc. of the IEEE Int. Symp. on Workload Characterization
Citations:33 - 0 self

Documents Related by Co-Citation

1091 The SPLASH-2 programs: Characterization and methodological considerations – Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Singh, Anoop Gupta - 1995
273 The PARSEC benchmark suite: Characterization and architectural implications – Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, Kai Li - 2008
35 Last Level Cache (LLC) performance of data-mining workloads on a CMP—A case study of parallel bioinformatics workloads – Aamer Jaleel, Matthew Mattina, Bruce Jacob - 2006
1004 Wattch: A Framework for Architectural-Level Power Analysis and Optimizations – David Brooks, Vivek Tiwari, Margaret Martonosi - 2000
149 Larrabee: a many-core x86 architecture for visual computing – Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Toni Juan, Pat Hanrahan - 2008
120 Optimization Principles and Application Performance Evaluation of a Multithreaded GPU Using CUDA Abstract – Shane Ryoo, Christopher I. Rodrigues, Sara S. Baghsorkhi, Sam S. Stone
53 MineBench: A Benchmark Suite for Data Mining Workloads – Ramanathan Narayanan, Berkin Özıs. Ikyılmaz, Joseph Zambreno, Gokhan Memik, Alok Choudhary - 2006
215 CACTI 3.0: An Integrated Cache Timing, Power, and Area Model – Premkishore Shivakumar, Norman P. Jouppi, Premkishore Shivakumar - 2001
118 A powerperformance simulator for interconnection networks – H S Wang, X Zhu, L S Peh, S Malik, “Orion - 2002
11 Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors – Christopher J. Hughes, Radek Grzeszczuk, Eftychios Sifakis, Daehyun Kim, Sanjeev Kumar, Andrew P. Selle, Jatin Chhugani, Matthew Holliman, Yen-kuang Chen - 2007
33 Recognition, Mining and Synthesis Moves Computers to the Era of Tera – Pradeep Dubey - 2005
599 Pin: building customized program analysis tools with dynamic instrumentation – Chi-keung Luk, Robert Cohn, Robert Muth, Harish Patil, Artur Klauser, Geoff Lowney, Steven Wallace, Vijay Janapa, Reddi Kim Hazelwood - 2005
12 An 80-tile 1.28 TFLOPS network-on-chip – S Vangal - 2007
397 Principles and Practices of Interconnection Networks – W J Dally, B Towles - 2004
146 The M5 simulator: Modeling networked systems – Nathan L. Binkert, Ronald G. Dreslinski, Lisa R. Hsu, Kevin T. Lim, Ali G. Saidi, Steven K. Reinhardt - 2006
5 On-chip interconnection networks of the TRIPS chip – P Gratz, C Kim, K Sankaralingam, H Hanson, P Shivakumar, S Keckler, D Burger - 2007
241 Transactional Locking II – Dave Dice, Ori Shalev, Nir Shavit - 2006
179 McRT-STM: a High Performance Software Transactional Memory System for a Multi-Core Runtime – Bratin Saha, Ali-reza Adl-tabatabai, Richard L. Hudson, Chi Cao Minh, Benjamin Hertzberg - 2006
795 MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems – Chunho Lee, Miodrag Potkonjak, William H. Mangione-smith