A 0.9V 12mW 5MSPS algorithmic ADC with 77dB SFDR (2005)

by Jipeng Li , Gil-cho Ahn , Student Member , Dong-young Chang , Un-ku Moon , Senior Member
Venue:IEEE J. Solid-State Circuits
Citations:5 - 3 self

Active Bibliography

15 Background calibration techniques for multistage pipelined ADCs with digital redundancy – Jipeng Li, Student Member, Un-ku Moon, Senior Member - 2003
9 Radix-based digital calibration technique for multi-stage ADC – Dong-young Chang, Un-ku Moon - 2002
3 Sub-1-v design techniques for highlinearity multistage/pipelined analog-to-digital converters – Dong-young Chang, Gil-cho Ahn, Student Member, Un-ku Moon, Senior Member - 2005
7 A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration – Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis - 2004
Wideband High-Performance Sigma-Delta Modulators for High-Speed Communications – Yi Yin - 2006
Digitally Calibrated Analog-to-Digital Converters in Deep Sub-micron – Cheongyuen (bill Tsang, All Rights Reserved, Cheongyuen William Tsang, Cheongyuen William Tsang, Cheongyuen William Tsang - 2008
Committee: – Cheongyuen William Tsang, Professor Borivoje Nikolić, Professor Paul, R. Gray - 2003
5 A 0.6V 82-dB delta-sigma audio ADC using switched-RC integrators – Gil-cho Ahn, Student Member, Dong-young Chang, Matthew E. Brown, Gábor C. Temes, Life Fellow, Un-ku Moon, Senior Member - 2005
7 A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique – Jipeng Li, Un-ku Moon, Senior Member - 2004
5 Background interstage gain calibration technique for pipelined ADCs – John P. Keane, Student Member, Paul J. Hurst, Stephen H. Lewis, John P. Keane - 2005
Least Mean Square Adaptive Digital Background – Calibration Of Pipelined, Yun Chiu, Cheongyuen W. Tsang, Student Member, Student Member, Borivoje Nikolić, Paul R. Gray - 2004
Research Article A Simple Technique for Fast Digital Background Calibration of A/D Converters – Francesco Centurelli, Pietro Monsurrò, Ro Trifiletti
8 A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC – Eric Siragusa, Ian Galton - 2004
22 Background Digital Calibration Techniques for Pipelined ADC's – Un-ku Moon, Bang-sup Song - 1997
1 An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage – Imran Ahmed, Student Member, David A. Johns
A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter – Andrew Abo And, Abstract—a -v, Ms/s Pipeline Analog-to-digital
2 A 12-Bit 200-MHz CMOS ADC – Bibhu Datta Sahoo, Behzad Razavi
unknown title – unknown authors
unknown title – unknown authors