Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors (1996)

by Kenneth M. Wilson , Kunle Olukotun , Mendel Rosenblum
Citations:35 - 2 self

Active Bibliography

66 Memory-System Design Considerations For Dynamically-Scheduled Microprocessors – Keith Istvan Farkas - 1997
15 Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches – Dimitrios Stiliadis, Anujan Varma - 1994
About Effective Cache Miss . . . – Andre Seznec, Fabien Lloansi - 1995
2 Hardware And Software Mechanisms For Reducing Load Latency – Todd Michael Austin - 1996
46 Out-of-Order Vector Architectures – Roger Espasa, Mateo Valero, James E. Smith - 1997
Loop Optimization Techniques On Multi-Issue Architectures – Dan Richard Kaiser - 1994
76 The Microarchitecture of Superscalar Processors – James E. Smith, Gurindar S. Sohi - 1995
3 Microarchitectural Innovations: Boosting Microprocessor Performance beyond Semiconductor Technology Scaling – Andreas Moshovos, Gurindar, S. Sohi - 2001
Performance impact of the L2 contention on out-of-order execution superscalar processors – AndrĂ© Seznec, et al. - 1997
Exploring Design Alternatives for a Highly-Integrated, Wide-Issue, Microprocessor-Based System – David H. Albonesi, Israel Koren
85 Complexity/Performance Tradeoffs with Non-Blocking Loads – Keith I. Farkas, Norman P. Jouppi - 1994
113 The Multiscalar Architecture – Manoj Franklin - 1993
45 Compiling for the Multiscalar Architecture – T. N. Vijaykumar - 1998
Reducing Compulsory and Capacity Misses – Norman P. Jouppi - 1990
3 Evaluating the Performance of Active Cache Management Schemes – Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson - 1998
3 Latency Tolerance For Dynamic Processors – James E. Bennett, Michael J. Flynn - 1996
Critical Loads -- Classification, . . . – Srikanth T. Srinivasan - 2001
An SRAM Main Memory Model – Pierre Salverda, Pierre Salverda - 1997
6 Preliminary Investigation of the RAMpage Memory Hierarchy – Philip Machanick, Pierre Salverda - 1998