An Analysis of U.S. Patent #5,243,538 “Comparison and Verification System for Logic Circuits and Method Thereof,” (1994)

by Randal E. Bryant

Active Bibliography

894 Symbolic Boolean manipulation with ordered binary-decision diagrams – Randal E Bryant - 1992
2976 Graph-based algorithms for Boolean function manipulation – Randal E. Bryant - 1986
587 Symbolic Model Checking: 10^20 States and Beyond – J. R. Burch, E. M. Clarke, K. L. McMillan, D. L. Dill, L. J. Hwang - 1992
2474 Compositional Model Checking – E. M. Clarke, D. E. Long, K. L. Mcmillan - 1999
620 Counterexample-guided Abstraction Refinement – Edmund Clarke, Orna Grumberg, Somesh Jha, Yuan Lu, Helmut Veith - 2000
719 Symbolic Model Checking without BDDs – Armin Biere , Alessandro Cimatti, Edmund Clarke, Yunshan Zhu - 1999
454 Efficient implementation of a BDD package – Karl S. Brace, Richard L. Rudell, Randal E. Bryant - 1991
237 On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication – R E Bryant - 1991
426 Decision-Theoretic Planning: Structural Assumptions and Computational Leverage – Craig Boutilier, Thomas Dean, Steve Hanks - 1999