A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing (1998)
Cached
Download Links
- [home.eng.iastate.edu]
- [www.hwswworld.com]
- DBLP
Other Repositories/Bibliography
by
Chris C. N. Chu
,
D. F. Wong
| Venue: | IEEE Transactions on Comput. Aided Des. Integrated Circuits Syst |
| Citations: | 3 - 0 self |
Document Versions
| A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing –Chris C. N. Chu, et al. |
| A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing –Chris C. N. Chu, D. F. Wong — 1998 — IEEE Transactions on Comput. Aided Des. Integrated Circuits Syst |
