A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing (1998)

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by Chris C. N. Chu , D. F. Wong
Venue:IEEE Transactions on Comput. Aided Des. Integrated Circuits Syst
Citations:5 - 2 self

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13 A new approach to simultaneous buffer insertion and wire sizing – Chris C. N. Chu, D. F. Wong - 1997
A New Approach toSimultaneous Bu er Insertion and Wire Sizing – Chris C. N. Chu, D. F. Wong
45 Closed form solution to simultaneous buffer insertion/sizing and wire sizing – Chris C. N. Chu, D. F. Wong - 1997
7 Theory and Algorithm of Local-Refinement Based Optimization with Application to Device and Interconnect Sizing – Jason Cong, Lei He - 1999
11 Greedy wire-sizing is linear time – Chris C. N. Chu, Martin D. F. Wong - 1998
11 An efficient and optimal algorithm for simultaneous buffer and wire sizing – Chris C. N. Chu, D. F. Wong - 1999
9 A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing – Chris C. N. Chu, D. F. Wong - 1999
7 An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs – Jason Cong, Lei He - 1997
38 GLOBAL INTERCONNECT SIZING AND SPACING WITH CONSIDERATION OF COUPLING CAPACITANCE – Jason Cong, et al. - 1997
69 An Interconnect-Centric Design Flow for Nanometer Technologies – Jason Cong - 1999
80 Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation – Chung-ping Chen, Chris C. N. Chu, D. F. Wong - 1997
5 Modeling and Optimization of VLSI Interconnects – Lei He - 1999
1 Modeling and Layout Optimization of VLSI Devices and Interconnects in Deep Submicron Design – Jason Cong - 1997
7 Theory and Algorithm of Local-Refinement-Based Optimization with Application to Device and Interconnect Sizing – Jason Cong, Lei He - 1999
57 Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization – Takumi Okamoto , Jason Cong - 1996
6 Wire Width Planning for Interconnect Performance Optimization – Jason Cong, Zhigang (David) Pan - 2002
22 Interconnect Performance Estimation Models for Design Planning – Jason Cong, Zhigang (David) Pan - 2001
8 Interconnect Performance Estimation Models for Synthesis and Design Planning – Jason Cong , Zhigang Pan
25 Interconnect Layout Optimization under Higher-Order RLC Model for MCM Designs – Jason Cong, Cheng-Kok Koh, Patrick H. Madden - 1997