|
748
|
MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems
– Chunho Lee, Miodrag Potkonjak, William H. Mangione-smith
|
|
70
|
Processor acceleration through automated instruction set customization
– Nathan Clark, Hongtao Zhong, Scott Mahlke
- 2003
|
|
20
|
Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication
– Peter G. Sassone, D. Scott Wills
- 2004
|
|
81
|
The Performance Potential of Data Dependence Speculation & Collapsing
– Yiannakis Sazeides, Yiannakis Sazeides, Stamatis Vassiliadis, Stamatis Vassiliadis, James E. Smith, James E. Smith
- 1996
|
|
23
|
From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation
– Sami Yehia, Olivier Temam
- 2004
|
|
34
|
Automatic generation of application specific processors
– D Goodwin, D Petkov
- 2003
|
|
8
|
et al. Synthesis of custom processors based on extensible platforms
– F Sun
- 2002
|
|
95
|
Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints
– Kubilay Atasu, et al.
- 2003
|
|
11
|
et al. An architecture framework for transparent instruction set customization in embedded processors
– N Clark
- 2005
|
|
44
|
Instruction Pre-Processing in Trace Processors
– Quinn Jacobson, James E. Smith
- 1999
|
|
171
|
A High-Performance Microarchitecture with Hardware-Programmable Functional Units
– Rahul Razdan, Michael D. Smith
- 1994
|
|
24
|
DISC: The dynamic instruction set computer
– Michael J. Wirthlin, Brad L. Hutchings
- 1995
|
|
156
|
Processor Reconfiguration Through Instruction Set Metamorphosis: Compiler and Architecture
– Peter Athanas, Harvey F. Silverman
- 1993
|
|
321
|
Garp: A MIPS Processor with a Reconfigurable Coprocessor
– John R. Hauser , John Wawrzynek
- 1997
|
|
375
|
Mibench: A free, commercially representative embeddedbenchmarksuite,”inWWC’01:ProceedingsoftheWorkload Characterization, 2001.WWC-4.2001IEEEInternational Workshop
– J S Ringenberg M R Guthaus, T M Austin D Ernst, T Mudge, R B Brown
|
|
24
|
High-performance 3-1 interlock collapsing ALU’s
– J Phillips, S Vassiliadis
- 1994
|
|
9
|
et al. Application-specific processing on a general-purpose core via transparent instruction set customization
– N Clark
- 2004
|
|
8
|
Cycle-time Aware Architecture Synthesis of Custom Hardware Accelerators
– Shail Aditya, Mukund Sivaraman, Mukund Sivaraman
- 2002
|
|
17
|
Using dynamic binary translation to fuse dependent instructions
– Shiliang Hu, James E. Smith
- 2004
|