Potential-Driven Statistical Ordering of Transformations (1997)

by Inki Hong , Darko Kirovski , Miodrag Potkonjak
Venue:Design Automation Conference
Citations:8 - 5 self

Active Bibliography

2 Behavioral Level Guidance Using Property-Based Design Characterization by – Lisa Marie Guerra, Lisa Marie Guerra, Lisa Marie Guerra - 1996
6 A Methodology for Guided Behavioral-Level Optimization – Lisa Guerra, Miodrag Potkonjak, Jan Rabaey - 1998
3 Divide-and-Conquer Techniques for Global Throughput Optimization – Lisa Guerra, Miodrag Potkonjak, Jan Rabaey - 1996
Symbolic Debugging of Optimized Behavioral Specifications – Darko Kirovski, M. Potkonjak - 1999
10 Considering Testability at Behavioral Level: Use of Transformations for Partial Scan Cost Minimization Under Timing and Area Constraints – Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy - 1995
3 FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-flow Intensive Behavioral Descriptions – Ganesh Lakshminarayana, Niraj K. Jha, Ganeshlakshminarayana Andnirajk Jha - 1998
9 Low-power architectural synthesis and the impact of exploiting locality – Renu Mehra, Lisa M. Guerra, Jan M. Rabaey - 1996
Hot Potato Techniques in High Level Synthesis – Miodrag Potkonjak, Sujit Dey - 1995
7 Power Optimization using Divide-and-Conquer Techniques for Minimization of the Number of Operations – Inki Hong , Miodrag Potkonjak, Ramesh Karri - 1997
167 Optimizing Power Using Transformations – Anantha P. Chandrakasan, Miodrag Potkonjak, Renu Mehra, Jan Rabaey, Robert W. Brodersen - 1995
1 Properties and Algorithms for Unfolding of Probabilistic Data-flow Graphs – Sissades Tongsima , Timothy W. O'Neil, Chantana Chantrapornchai, Edwin H.-M. Sha
11 Coordinated Parallelizing Compiler Optimizations and High-Level Synthesis – Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alex Nicolau - 2002
2 High-Level Synthesis of a 1 Mbps Direct-Sequence Spread-Spectrum RAKE Receiver – Fermín Bueno, Johnny Öberg, Anshul Kumar, Mats Torkelsson, Ferm'in Bueno Johnny
2 Exploiting Locality for Low-Power Design – Renu Mehra, Lisa Guerra, Jan Rabaey - 1996
4 Low Power High Level Synthesis By Increasing Data Correlation – Dongwan Shin, Kiyoung Choi - 1997
7 An Integrated CAD Environment for Low-Power Design – Paul Landman, Renu Mehra, Jan M. Rabaey - 1995
7 A Partitioning Scheme for Optimizing Interconnect Power – Renu Mehra, Lisa M. Guerra, Jan M. Rabaey - 1997
1 Behavioral Profiling Based High Level Power Estimation Methodologies for VLSI ASIC and FPGA Synthesis – Srinivas Katkoori
9 Automating High Level Control Flow Transformations For DSP Memory Management – Michaël F.X.B. van Swaaij, Micha F. X. B, Francky V.M. Catthoor, Hugo J. De Man, Swaaij Frank, H. M. Franssen, Francky V. M, Catthoor Hugo, J. De Man - 1992