Design Tradeoffs Using Truncated Multipliers in Fir Filter Implementations (2002)

by George Walters , E. George , Walters Iii , Michael Schulte
Citations:5 - 0 self

Active Bibliography

5 Variable-Correction Truncated Floating Point Multipliers – Michael J. Schulte, Kent E. Wires, James E. Stine - 2000
Design and Implementation of Truncated Multipliers for Precision Improvement and Its Application to a Filter Structure – R. Devarani, Mr. C. S. Manik, A Babu
International Journal of Electronics and Computer Science Engineering 627 Available Online at www.ijecse.org ISSN- 2277-1956 Traditional and Truncation schemes for Different Multiplier – Yogesh M. Motey, Tejaswini G. Panse
4 High-Speed Inverse Square Roots – Michael J. Schulte, Kent E. Wires - 1999
19 Reduced Power Dissipation Through Truncated Multiplication – Michael J. Schulte, James E. Stine, John G. Jansen - 1999
2 Combined Unsigned and Two's Complement Saturating Multipliers – Michael J. Schulte, Mustafa Gok, Pablo I. Balzola, Robert W. Brocato - 2000
4 Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation – Kent E. Wires, Michael J. Schulte, James E. Stine - 2001
0 TRUNCATED ON-LINE ARITHMETIC WITH APPLICATIONS TO COMMUNICATION SYSTEMS – Sridhar Rajagopal, Joseph R. Cavallaro - 2003
12 Parallel Saturating Fractional Arithmetic Units – Navindra Yadav, Michael Schulte, John Glossner - 1999
2 High-Speed Reciprocal Approximations – Michael J. Schulte, James E. Stine, Kent E. Wires - 1998
A Novel Architecture and a Systematic Graph-Based Optimization Methodology for Modulo Multiplication – Giorgos Dimitrakopoulos, Vassilis Paliouras
7 Integer Multiplication with Overflow Detection or Saturation – Michael J. Schulte, Pablo I. Balzola, Ahmet Akkas, Robert W. Brocato - 2000
ARITHMETIC UNITS FOR A HIGH PERFORMANCE DIGITAL SIGNAL PROCESSOR By – Michael Andrew Lai - 2004
13 Design and Implementation of the MorphoSys Reconfigurable Computing Processor – Ming-hau Lee, Hartej Singh, Guangming Lu, Nader Bagherzadeh, Fadi J. Kurdahi, Fadi, J. Kurdahi - 2000
3 Area Delay (A T ) Efficient Multiplier Based on an Intermediate Hybrid Signed--Digit (HSD--1) Representation – Jeng-jong J. Lue - 1999
Design of Optimal Reversible Carry Look-Ahead Adder with Optimal Garbage and Quantum Cost – Lafifa Jamal, Md. Shamsujjoha, Hafiz Md, Hasan Babu
1 Tradeoff Analysis of Integer Multiplier Circuits Implemented in FPGAs – M. A. Thornton, J. D. Gaiche, J. V. Lemieux
8 Design and Implementation of a 16 by 16 Low-Power Two's Complement Multiplier – Alexander Goldovsky, Bimal Patel, Michael Schulte, Ravi Kolagotla, Hosahalli Srinivas, Geoffrey Burns - 2000
Carry Prediction and Selection for Truncated Multiplication – Romain Michard, Arnaud Tisser, Nicolas Veyrat-charvillon