Single-Phase Source-Coupled Adiabatic Logic (1999)

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by Suhwan Kim , Marios C. Papaefthymiou
Venue:in Proceedings of International Symposium on Low-Power Electronics and Design
Citations:10 - 2 self

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2 Pipelined DSP Design with a True Single-Phase Energy-Recovering Logic Style – Suhwan Kim, Marios C. Papaefthymiou - 1999
11 True Single-Phase Energy-Recovering Logic for Low-Power, High-Speed VLSI – Suhwan Kim, Marios C. Papaefthymiou - 1998
4 Design, verification, and test of a true single-phase 8-bit adiabatic multiplier – Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou - 2001
8 A True Single-Phase 8-bit Adiabatic Multiplier – Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou - 2001
1 Analysis of Power-Clocked CMOS with Application to the – Design Of Energy-Recovery, Massoud Pedram
Adiabatic CMOS Circuit Design: Principles and Examples – unknown authors
1 An Energy-Aware Active Smart Card – Russell Tessier, David Jasinski, Atul Maheshwari, Weifeng Xu, Wayne Burleson, Senior Member
Investigating the DPA-Resistance Property of Charge Recovery Logics – Amir Moradi, Mehrdad Khatir, Mahmoud Salmasizadeh, Mohammad T. Manzuri Shalmani
3.1p On Optimality of Adiabatic Switching in MOS Energy-Recovery Circuit – Baohua Wang, Pinaki Mazumder
Efficiency of Adiabatic Logic for Low-Power, Low-Noise VLSI – Hamid Mahmoodi-Meimand, Ali Afzali-kusha
2 Energy Recovery Design for Low-Power ASICs – Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou
4 A Resonant Clock Generator for Single-Phase Adiabatic Systems – Conrad H. Ziesler - 2001
1 DESIGNING LOW-POWER ENERGY RECOVERY ADDERS BASED ON PASS TRANSISTOR LOGIC – D. Soudris, V. Pavlidis, A. Thanailakis
Secure Adiabatic Logic: a Low-Energy DPA-Resistant Logic Style – Mehrdad Khatir, Amir Moradi
Design of Low Power CMOS Circuits with Energy Recovery – Xunwei Wu, Guoqiang Hang, M. Pedram
This project was sponsored in part by NNSF of China (Grant No.69973039) and NSF of USA (Grant No. – Low Power Dcvslcircuits, Xunwei Wu, Guoqiang Hang, Massoud Pedram
3 480-GMACS/mW Resonant Adiabatic Mixed-Signal Processor Array for Charge-Based Pattern Recognition – Rafal Karakiewicz, Student Member, Roman Genov, Gert Cauwenberghs, Senior Member - 2007
Design and Analysis of Low Power Full Adder Using Adiabatic Technique – P. Sreenivasulu, M. V. Narasimha Reddy, G. V. K. Varaprasad Swamy
Reversible Energy Recovery Logic Circuits and Its 8-Phase Clocked Power Generator for Ultra-Low-Power Applications – Joonho Lim Dong-Gyu, Joonho Lim +a, Dong-gyu Kim, Soo-ik Chae - 1999