A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter

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by Andrew Abo And , Abstract—a -v , Ms/s Pipeline Analog-to-digital

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5 A 0.9V 12mW 5MSPS algorithmic ADC with 77dB SFDR – Jipeng Li, Gil-cho Ahn, Student Member, Dong-young Chang, Un-ku Moon, Senior Member - 2005
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9 An Audio ADC Delta-Sigma Modulator with 100-dB Peak SINAD and 102-dB DR Using a Second-Order Mismatch-Shaping DAC – Eric Fogleman, Jared Welz, Student Member, Ian Galton - 2001
8 Simplified Logic for First-Order and Second-Order Mismatch-Shaping Digital-to-Analog Converters – Jared Welz, Ian Galton, Eric Fogleman - 2001
Design Techniques for Low-Voltage and Low-Power Analog-to-Digital Converters – Un-ku Moon, Gil Cho Ahn - 2005