A Self-Timed Multiplier using Conditional Evaluation

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by Bartlett And Grass , V. A. Bartlett , E. Grass
Venue:Proc. PATMOS’98, 8th Int. Workshop on Power, Timing, Modeling, Optimization and Simulation, Lyngby
Citations:1 - 1 self

Active Bibliography

59 An introduction to asynchronous circuit design – Al Davis, Steven M. Nowick - 1997
3 Multipliers and datapaths – Michael Flynn, Hesham Al-twaijry, Michael Flynn, Hesham Al-twaijry, Michael Flynn - 1994
2 Performance/Area Tradeoffs in Booth Multipliers – Hesham Al-Twaijry, Hesham Al-twaijry, Hesham Al-twaijry, Michael Flynn, Michael Flynn, Michael Flynn - 1995
3 Mixed-swing Quadrail for Low Power Dual-rail Domino Logic – Bharath Ramasubramanian, Herman Schmit, L. Richard Carley - 1999
6 Implication graph based domino logic synthesis – Ki-wook Kim, C. L. Liu, Sung-mo Kang - 1999
5 Algorithm-based low-power and high-performance multimedia signal processing – K. J. Ray Liu, Senior Member, An-yeu Wu - 1998
Practical Performance/Power Alternatives within an Existing CMOS Technology Generation – Kerry Bernstein, John E. Bertsch, William F. Clark, John J. Ellis-monaghan, Larry G. Heller, Edward J. Nowak
Protocol Selection, Implementation, and Analysis for Asynchronous Circuits – Eric Robert Peskin, Erik Brunvand, Al Davis, Ganesh Gopalakrishnan, Christian Schlegel, Thomas C. Henderson, David S. Chapman - 2002
19 Self-Timed Logic Using Current-Sensing Completion Detection (CSCD) – Mark E. Dean, David L. Dill, Mark Horowitz - 1994
64 Four-Phase Micropipeline Latch Control Circuits – Stephen B. Furber, Paul Day - 1996
1 Low-Power Array Multipliers with Transition-Retaining Barriers – Enric Musoll, Jordi Cortadella - 1995
1 ARTICLE IN PRESS – S. C. Smith - 2004
2 Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks – Dhireesha Kudithipudi, Eugene John - 2005
19 Reduced Power Dissipation Through Truncated Multiplication – Michael J. Schulte, James E. Stine, John G. Jansen - 1999
Design of a low power and high performance digital multiplier – unknown authors
Asynchronous Multipliers with Variable-Delay Counters – Gianluca Cornetta Computer, Gianluca Cornetta - 2001
1 http://async.org.uk Self-Timed SRAM with Smart Latency Bundling Self-Timed SRAM with Smart Latency Bundling – Abdullah Baz, Delong Shang, Fei Xia, Reza Ramezani, Robin Emery, Alex Yakovlev, Abdullah Baz, Delong Shang, Fei Xia, Reza Ramezani, Robin Emery, Alex Yakovlev
1 A Multi-Radix Approach to Asynchronous Division – Gianluca Cornetta, Jordi Cortadella
An Asynchronous Floating-Point Multiplier – Basit Riaz Sheikh, Rajit Manohar