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Maximum Likelihood Estimation: A Single and Multi-objective Entropy Optimization Approach
– Bablu Samanta
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Optimal Allocation of Local Feedback in Multistage Amplifiers via Geometric Programming
– Joel Dawson Stephen, Stephen P. Boyd, Maria Del Mar Hershenson, Thomas H. Lee
- 2000
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11
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Bandwidth Extension in CMOS with Optimized On-Chip Inductors
– Sunderarajan S. Mohan, Maria del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee
- 2000
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5
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A general approach to sparse basis selection: Majorization, concavity, and affine scaling
– K. Kreutz-Delgado, B. D. Rao
- 1997
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7
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Optimal allocation of local feedback in multistage amplifiers via geometric programming
– Joel L. Dawson, Stephen P. Boyd, Maria Del Mar Hershenson, Thomas H. Lee
- 2001
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36
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Optimal design of a CMOS op-amp via geometric programming
– Maria Del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee
- 2001
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69
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Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation
– Chung-ping Chen, Chris C. N. Chu, D. F. Wong
- 1997
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unknown title
– unknown authors
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Chip and Package Co-Design of Clock Networks
– Qing Zhu, Wayne Wei-ming Dai, David Helmbold, Martine Schlag
- 1995
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Bounded-Skew Clock and Steiner Routing Under Elmore Delay
– Jason Cong Andrew, Andrew B. Kahng, Cheng-kok Koh, C. -w. Albert Tsao
- 1995
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Crosstalk Noise Avoidance In Asynchronous Circuits
– Alexander Taubin, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno
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Hybrid Structured Clock Network Construction
– Haihua Su Sachin
- 2001
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Clock Tree Synthesis For Multi-Chip Modules
– Daksh Lehther And
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Clock-Tree Power Optimization based on RTL Clock-Gating Monica Donno
– Monica Donno Bulldast, Monica Donno, Alessandro Ivaldi
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1
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Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications
– Alexander Taubin, Alex Kondratyev, Luciano Lavagno, Jordi Cortadella
- 1998
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1
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Integrated placement and skew optimization for rotary clocking
– Ganesh Venkataraman, Jiang Hu, Frank Liu, C-n. Sze
- 2006
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6
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Minimizing Wirelength in Zero and Bounded Skew Clock Trees
– Moses Charikar, Jon Kleinberg, Ravi Kumar, Sridhar Rajagopalan, Amit Sahai, Andrew Tomkins
- 1999
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2
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Power Optimization in VLSI Layout: A Survey
– Massoud Pedram, Hirendu Vaishnav
- 1997
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1
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Moment-based techniques for RLC clock tree construction
– Daksh Lehther, Sachin S. Sapatnekar
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