On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis System (0)

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by Naren Narasimhan , Ranga Vemuri
Venue:Proceedings of 11th Conference on Theorem Proving in Higher Or der Logics (TPHOL'98
Citations:3 - 3 self

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7 Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis – Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri - 1998
13 Formal Synthesis in Circuit Design - A Classification and Survey – Ramayya Kumar, Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid - 1996
6 Formally Embedding Existing High Level Synthesis Algorithms – Dirk Eisenbiegler, Ramayya Kumar, Forschungszentrum Informatik - 1995
9 Implementation Issues about the Embedding of Existing High Level Synthesis Algorithms in HOL – Dirk Eisenbiegler, Christian Blumenröhr, Ramayya Kumar - 1996
20 Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment – Ramayya Kumar, Klaus Schneider, Thomas Kropf - 1993
1 Mechanizing in Higher-Order Logic Proofs of Correctness and Completeness for a Set of RTL Transformations – Elena Teica, Ranga Vemuri
5 Hierarchical Behavioral Partitioning for Multicomponent Synthesis – Nand Kumar, Vinoo Srinivasan, Ranga Vemuri, San Jose Ca - 1996
10 A Transformational Approach to Formal Digital System Design – Mats Larsson, Mats Larsson - 1993
2 RTBA : A Generic Bit-Sliced Bus Architecture for DataPath Synthesis – Kamlesh Rath, Ignacio Celis, Robert M. Wehrmeister, Steven D. Johnson - 1990
6 Modeling a Hardware Synthesis Methodology in Isabelle – David Basin, Stefan Friedrich - 1996
9 A Practical Methodology for the Formal Verification of RISC Processors – Sofiène Tahar, Ramayya Kumar - 1995
An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form – Philip Brisk, Ajay K. Verma, Paolo Ienne
2 Optimal polynomial-time interprocedural register allocation for high level synthesis and – Philip Brisk, Ajay K. Verma, Paolo Ienne
6 From VHDL to Efficient and First-Time-Right Designs: A Formal Approach – Peter F. A. Middelhoek, Sreeranga P. Rajan - 1986
2 An efficient representation for formal synthesis – Christian Blumenröhr, Dirk Eisenbiegler - 1997
2 Applicability of Formal Synthesis Illustrated via Scheduling – Christian Blumenröhr, Dirk Eisenbiegler, R. Kumar, Forschungszentrum Informatik - 1996
4 Codesign For Real-Time Video Applications – J. Wilberg - 1996
Transformations for Functional Verification of Synthesized Designs – William Bradley, Ranga R. Vemuri - 1995
A generic binding model for concurrently optimizing interconnection and functional units – En-Shou Chang, Daniel D. Gajski - 1997