Reduced Power Dissipation Through Truncated Multiplication (1999)

by Michael J. Schulte , James E. Stine , John G. Jansen
Venue:in IEEE Alessandro Volta Memorial Workshop on Low Power Design
Citations:15 - 5 self

Active Bibliography

4 Variable-Correction Truncated Floating Point Multipliers – Michael J. Schulte, Kent E. Wires, James E. Stine - 2000
6 Integer Multiplication with Overflow Detection or Saturation – Michael J. Schulte, Pablo I. Balzola, Ahmet Akkas, Robert W. Brocato - 2000
1 Combined Unsigned and Two's Complement Saturating Multipliers – Michael J. Schulte, Mustafa Gok, Pablo I. Balzola, Robert W. Brocato - 2000
5 Design and Implementation of a 16 by 16 Low-Power Two's Complement Multiplier – Alexander Goldovsky, Bimal Patel, Michael Schulte, Ravi Kolagotla, Hosahalli Srinivas, Geoffrey Burns - 2000
Carry Prediction and Selection for Truncated Multiplication – Romain Michard, Arnaud Tisser, Nicolas Veyrat-charvillon
2 A Custom Computing Framework for Orientation and Photogrammetry – Paul D. Fiore - 2000
3 High-Speed Inverse Square Roots – Michael J. Schulte, Kent E. Wires - 1999
4 Design Tradeoffs Using Truncated Multipliers in Fir Filter Implementations – George Walters, E. George, Walters Iii, Michael Schulte - 2002
3 Technology scaling effects on multipliers – Hesham A. Al-twaijry, Michael J. Flynn - 1996
8 A Compact High-Speed (31,5) Parallel Counter Circuit Based on Capacitive Threshold-Logic Gates – Y. Leblebici, H. Özdemir, A. Kepkep, U. Çilingiroglu, U. Cilingiro Glu - 1996
8 Automatic synthesis of compressor trees: reevaluating large counters – Ajay K. Verma, Paolo Ienne
Arithmetic, pp. 168--174, IEEE Computer Society, 1997. [41] M. J. Schulte and E. E. Swartzlander, "Hardware Designs for Exactly Rounded Elementary Functions," – Ieee Transactions On, E. E. Swartzl, A. G. Alexopoulos, The Sign/logarithm Number System
1 Combined Multiplication and Sum-of-Squares Units – Michael J. Schulte, Louis Marquette, Shankar Krithivasan, E. George, Walters Iii, John Glossner - 2003
International Journal of Electronics and Computer Science Engineering 615 Available Online at www.ijecse.org ISSN- 2277-1956 Design of Low-Error Fixed-Width Modified Booth Multiplier – Amudha M, Sivasubramanian K
11 Parallel Saturating Fractional Arithmetic Units – Navindra Yadav, Michael Schulte, John Glossner - 1999
2 Integer Multiplication With Overflow Detection Or Saturation – Mustafa Gok, J. Schulte, Prof Bruce, D. Fritchman - 2000
13 A New Design Technique for Column Compression Multipliers – Zhongde Wang, G. A. Jullien, W. C. Miller - 1995
3 Area Delay (A T ) Efficient Multiplier Based on an Intermediate Hybrid Signed--Digit (HSD--1) Representation – Jeng-jong J. Lue - 1999
3 Combined Unsigned and Two's Complement Squarers – Kent E. Wires, Michael J. Schulte, Louis P. Marquette, Pablo I. Balzola - 1999