Reduced Power Dissipation Through Truncated Multiplication (1999)

by Michael J. Schulte , James E. Stine , John G. Jansen
Venue:in IEEE Alessandro Volta Memorial Workshop on Low Power Design
Citations:19 - 5 self

Active Bibliography

5 Variable-Correction Truncated Floating Point Multipliers – Michael J. Schulte, Kent E. Wires, James E. Stine - 2000
2 Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks – Dhireesha Kudithipudi, Eugene John - 2005
International Journal of Electronics and Computer Science Engineering 627 Available Online at ISSN- 2277-1956 Traditional and Truncation schemes for Different Multiplier – Yogesh M. Motey, Tejaswini G. Panse
7 Integer Multiplication with Overflow Detection or Saturation – Michael J. Schulte, Pablo I. Balzola, Ahmet Akkas, Robert W. Brocato - 2000
2 Combined Unsigned and Two's Complement Saturating Multipliers – Michael J. Schulte, Mustafa Gok, Pablo I. Balzola, Robert W. Brocato - 2000
Design and Implementation of Truncated Multipliers for Precision Improvement and Its Application to a Filter Structure – R. Devarani, Mr. C. S. Manik, A Babu
7 Design and Implementation of a 16 by 16 Low-Power Two's Complement Multiplier – Alexander Goldovsky, Bimal Patel, Michael Schulte, Ravi Kolagotla, Hosahalli Srinivas, Geoffrey Burns - 2000
1 Using truncated multipliers in DCT and IDCT hardware accelerators – E. George Walters, III, Mark G. Arnold, Michael J. Schulte - 2003
Carry Prediction and Selection for Truncated Multiplication – Romain Michard, Arnaud Tisser, Nicolas Veyrat-charvillon
2 A Custom Computing Framework for Orientation and Photogrammetry – Paul D. Fiore - 2000
International Journal of Electronics and Computer Science Engineering 615 Available Online at ISSN- 2277-1956 Design of Low-Error Fixed-Width Modified Booth Multiplier – Amudha M, Sivasubramanian K
4 High-Speed Inverse Square Roots – Michael J. Schulte, Kent E. Wires - 1999
5 Design Tradeoffs Using Truncated Multipliers in Fir Filter Implementations – George Walters, E. George, Walters Iii, Michael Schulte - 2002
4 Technology Scaling Effects on Multipliers – Hesham Al-Twaijry, Michael J. Flynn - 1996
8 A Compact High-Speed (31,5) Parallel Counter Circuit Based on Capacitive Threshold-Logic Gates – Y. Leblebici, H. Ă–zdemir, A. Kepkep, U. Çilingiroglu, U. Cilingiro Glu - 1996
8 Automatic synthesis of compressor trees: reevaluating large counters – Ajay K. Verma, Paolo Ienne
Arithmetic, pp. 168--174, IEEE Computer Society, 1997. [41] M. J. Schulte and E. E. Swartzlander, "Hardware Designs for Exactly Rounded Elementary Functions," – Ieee Transactions On, E. E. Swartzl, A. G. Alexopoulos, The Sign/logarithm Number System
Transform with a Fixed Booth Multiplier and Its Probabilistic Estimation – Ajeesh K N
1 Transitionactivity aware design of reduction-stages for parallel multipliers – Saeeid Tahmasbi Oskuii - 2007