New Algorithms for Gate Sizing: A Comparative Study (1996)

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by Olivier Coudert , Ramsey Haddad , Srilatha Manne
Venue:IN DAC
Citations:38 - 1 self

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31 Gate Sizing for Constrained delay/power/area optimization – Olivier Coudert - 1997
4 Integrated Resynthesis for Low Power – Olivier Coudert , Ramsey Haddad - 1996
109 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
21 Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint – Manjit Borah, Robert Michael Owens, Mary Jane Irwin - 1995
408 Multiobjective Optimization Using Nondominated Sorting in Genetic Algorithms – N. Srinivas, Kalyanmoy Deb - 1994
299 Direct least Square Fitting of Ellipses – Andrew Fitzgibbon , Maurizio Pilu, Robert B. Fisher - 1998
107 An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization – Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-mo Kang - 1993
15 Optimizing dominant time constant in RC circuits – Lieven Vandenberghe, Stephen Boyd, Abbas El Gamal - 1996
260 An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches – Changkyu Kim, Doug Burger, Stephen W. Keckler - 2002