New Algorithms for Gate Sizing: A Comparative Study (1996)

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by Olivier Coudert , Ramsey Haddad , Srilatha Manne
Venue:IN DAC
Citations:29 - 0 self

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102 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
19 Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint – Manjit Borah, Robert Michael Owens, Mary Jane Irwin - 1995
5 Modeling and Optimization of VLSI Interconnects – Lei He - 1999
19 A New Statistical Optimization Algorithm for Gate Sizing – Murari Mani, Michael Orshansky
15 Optimizing dominant time constant in RC circuits – Lieven Vandenberghe, Stephen Boyd, Abbas El Gamal - 1996
16 Timing and Area Optimization for Standard-Cell VLSI Circuit Design – Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj - 1995
90 An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization – Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-mo Kang - 1993
5 Computing the Entire Active Area / Power Consumption versus Delay Trade-off Curve for Gate Sizing with a Piecewise Linear Simulator – Michel R.C.M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess - 1994
8 Power-Delay Optimizations in Gate Sizing – Sachin S. Sapatnekar, Weitong Chuang - 2000
1 Layout driven timing optimization by generalized DeMorgan transform – Supratik Chakraborty, Rajeev Murgai
5 Mixed Swing Techniques for Low Energy/Operation Datapath Circuits – Ram Kumar Krishnamurthy - 1997
16 An Efficient Approach To Simultaneous Transistor And Interconnect Sizing – Jason Cong, Lei He - 1996
10 Optimization of Custom MOS Circuits by Transistor Sizing – Andrew R. Conn , Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandu Visweswariah - 1996
28.3 Novel Sizing Algorithm for Yield Improvement under Process Variation in Nanometer Technology – Seung Hoon Choi, Bipul C. Paul, Kaushik Roy
7 An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs – Jason Cong, Lei He - 1997
2 Combined transistor sizing with buffer insertion for timing optimization – Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim - 1998
12 Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization – Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn - 1995
28 Optimal Wire and Transistor Sizing for Circuits with Non-Tree Topology – Lieven Vandenberghe, Stephen Boyd, Abbas El Gamal - 1997
11 Area and Delay Trade-offs in the Circuit and Architecture . . . – Ian Kuon, Jonathan Rose - 2008